公开(公告)号：US09147461B1

公开(公告)日：2015-09-29

申请号：US14185264

申请日：2014-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youn Youn ,  So-Young Kim ,  Kwang-Sook Noh ,  Sang-Jae Rhee ,  Hyun-Chul Yoon ,  Yoon-Jae Lee ,  Jung-Bae Lee ,  Joo-Sun Choi

IPC: G11C11/40 ,  G11C11/406 ,  G11C8/18 ,  G06F11/10 ,  G11C11/22

CPC classification number: G11C11/40626 ,  G06F11/106 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/22 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.

Abstract translation: 半导体存储器件包括存储单元阵列和刷新控制电路。 刷新电路被配置为：在存储单元行从自刷新操作退出之后对存储单元行执行第二突发刷新操作，并且在存储单元行从退出之后不对存储单元行执行第二次突发刷新操作 自刷新操作。 刷新控制电路执行还是不执行第二脉冲串刷新操作是基于存储单元行的自刷新操作的输入时间与参考时间之间的比较。

公开(公告)号：US08675440B2

公开(公告)日：2014-03-18

申请号：US13754950

申请日：2013-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Cheol Lee ,  Jung-Bae Lee

IPC: G11C5/14

CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

Abstract: A method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors includes controlling the deep power down mode in the multi-port semiconductor memory such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

Abstract translation: 在具有连接到多个处理器的多个端口的多端口半导体存储器中控制深度掉电模式的方法包括控制多端口半导体存储器中的深度掉电模式，使得深度功率的激活/去激活 根据通过多个端口中的各个端口施加的信号确定下降模式。

公开(公告)号：US08988962B2

公开(公告)日：2015-03-24

申请号：US13749687

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Ho Shin ,  Jung-Bae Lee ,  Min-Jeung Cho

IPC: G11C7/00 ,  G11C11/402 ,  G11C11/406

CPC classification number: G11C11/402 ,  G11C11/40618

Abstract: A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

Abstract translation: 公开了一种刷新电路和包括刷新电路的半导体存储器件。 刷新电路包括模式寄存器，刷新控制器和多路复用器电路。 模式寄存器生成具有与要进行刷新操作的存储体有关的信息的模式寄存器信号。 刷新控制器基于自刷新命令和振荡信号产生自刷新活动命令和自刷新地址。 多路复用器电路可以包括多个多路复用器。 每个复用器响应于模式寄存器信号的位选择一个活动命令和自刷新活动命令。 每个多路复用器基于所选择的命令生成行活动信号，并且选择外部地址和自刷新地址之一以生成行地址。

公开(公告)号：US20140016421A1

公开(公告)日：2014-01-16

申请号：US13936057

申请日：2013-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Sik Kim ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C7/00 ,  G11C11/40 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4076 ,  G11C29/50016

Abstract: A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band.

Abstract translation: 一种存储刷新周期信息从而调节刷新周期的半导体存储器件及其操作方法。 半导体存储器件包括单元阵列和刷新信息存储单元。 单元阵列包括一个或多个单元区域，每个单元区域具有多个存储单元。 刷新信息存储单元被配置为存储包括与每个单元区域相对应的第一刷新周期和包括第二刷新周期的第二信息的第一信息。 包括在每个单元区域中的存储单元根据第一刷新时间带中的第一信息在第一刷新周期被刷新，并且在第二刷新周期中根据第二刷新时间段中的第二信息刷新。

公开(公告)号：US09449670B2

公开(公告)日：2016-09-20

申请号：US13960617

申请日：2013-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Sik You ,  Jung-Bae Lee

IPC: G11C11/40 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4091

CPC classification number: G11C11/402 ,  G11C11/406 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2211/4063 ,  G11C2211/4065

Abstract: A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a complementary bit line connected to a plurality of memory cells of a second memory block, a first switch configured to connect the bit line to the sense amplifier, and a second switch configured to connect the complementary bit line to the sense amplifier. The first switch is configured to electrically separate the bit line from the sense amplifier when the second memory block performs a refresh operation.

Abstract translation: 提供了一种半导体存储器件，其包括读出放大器，连接到第一存储器块的多个存储器单元的位线，连接到第二存储器块的多个存储器单元的互补位线，第一开关，被配置为 将位线连接到读出放大器，以及配置成将互补位线连接到读出放大器的第二开关。 第一开关被配置为当第二存储器块执行刷新操作时将位线与读出放大器电分离。

公开(公告)号：US09336851B2

公开(公告)日：2016-05-10

申请号：US14168793

申请日：2014-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo Yu ,  Jung-Bae Lee

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40603

Abstract: In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed.

Abstract translation: 在具有多个页面的存储装置中进行刷新的方法中，生成与在监视期间之后被更新的页面对应的候补刷新地址。 在监视期间监视是否处理候选刷新地址的活动命令。 如果在监视期间处理候选刷新地址的活动命令，则跳过该页面的计划刷新。 如果在监视期间没有处理候选刷新地址的活动命令，则执行预定的刷新操作。

公开(公告)号：US09082504B2

公开(公告)日：2015-07-14

申请号：US13936057

申请日：2013-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Sik Kim ,  Jung-Bae Lee

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/40

CPC classification number: G11C11/406 ,  G11C7/00 ,  G11C11/40 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4076 ,  G11C29/50016

Abstract: A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band.

Abstract translation: 一种存储刷新周期信息从而调节刷新周期的半导体存储器件及其操作方法。 半导体存储器件包括单元阵列和刷新信息存储单元。 单元阵列包括一个或多个单元区域，每个单元区域具有多个存储单元。 刷新信息存储单元被配置为存储包括与每个单元区域相对应的第一刷新周期和包括第二刷新周期的第二信息的第一信息。 包括在每个单元区域中的存储单元根据第一刷新时间带中的第一信息在第一刷新周期被刷新，并且在第二刷新周期中根据第二刷新时间段中的第二信息刷新。