公开(公告)号：US20180005688A1

公开(公告)日：2018-01-04

申请号：US15701636

申请日：2017-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-sung YOON ,  Doo-young KIM

IPC: G11C11/4076 ,  H01L29/423 ,  H01L27/108 ,  H03K5/15 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4096 ,  G11C2207/2272 ,  H01L27/108 ,  H01L29/42364 ,  H03K5/15066

Abstract: Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.

公开(公告)号：US20170125082A1

公开(公告)日：2017-05-04

申请号：US15206354

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-sung YOON ,  Doo-young KIM

IPC: G11C11/4076 ,  G11C11/4096 ,  H03K5/15 ,  H01L29/423 ,  H01L27/108

CPC classification number: G11C11/4076 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4096 ,  G11C2207/2272 ,  H01L27/108 ,  H01L29/42364 ,  H03K5/15066

Abstract: Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.