公开(公告)号：US11284240B2

公开(公告)日：2022-03-22

申请号：US16813146

申请日：2020-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Satish Kumar ,  Sukhdeep Singh ,  Suman Kumar ,  Avinash Bhat ,  Rahul Banerji ,  Naman Gupta ,  Seungil Yoon

IPC: H04W4/00 ,  H04W8/02 ,  H04W64/00 ,  H04W8/22

Abstract: A method and Network function for controlling an operation of a device based on a service provided to the device is provided. The method includes obtaining at least one of information about the service requested by the device, movement information of the device, or capability information of the device, determining a characteristic of the service provided to the device based on at least one of the information about the service, the movement information of the device, or the capability information of the device, generating service setting information for the service provided to the device based on the determined characteristic of the service, and transmitting, to an Access and Mobility Function (AMF), the service setting information.

公开(公告)号：US11042678B2

公开(公告)日：2021-06-22

申请号：US16664792

申请日：2019-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naman Gupta ,  Vinayak Kini ,  Hongda Lu

IPC: G06F30/327 ,  G06K9/62 ,  G06N3/04 ,  G06F1/10 ,  G06F30/39 ,  G06F30/396

Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.