Semiconductor integrated circuit device and method of providing bias power to the same

    公开(公告)号:US12156400B2

    公开(公告)日:2024-11-26

    申请号:US17740635

    申请日:2022-05-10

    Abstract: A semiconductor integrated circuit device includes a standard cell on a substrate, an one time programmable (OTP) memory structure at an edge portion of the standard cell, and a program transistor outside of the standard cell at a position adjacent to the edge portion of the standard cell at which the OTP memory structure is provided, the program transistor being electrically connected to the OTP memory structure. The OTP memory structure includes a first anti-fuse and a second anti-fuse. When a program voltage is applied to the program transistor and a bias power voltage is applied to the OTP memory structure, each of the first anti-fuse and the second anti-fuse becomes shorted and the bias power voltage is provided to the standard cell.

    One-time programmable (OTP) memory device and method of operating an OTP memory device

    公开(公告)号:US11882696B2

    公开(公告)日:2024-01-23

    申请号:US17558884

    申请日:2021-12-22

    CPC classification number: H10B20/20 G11C17/146 G11C17/16 G11C17/18

    Abstract: A one-time programmable (OTP) memory device includes an access transistor, a word line, a voltage line, a well, a first filling oxide layer, a first semiconductor layer, and a bit line. The access transistor includes a gate structure on a substrate, and first and second impurity regions at portions of the substrate adjacent to the gate structure. The word line is electrically connected to the gate structure. The voltage line is electrically connected to the first impurity region. The well is formed at an upper portion of the substrate, and is doped with impurities having a first conductivity type. The first filling oxide layer is formed on the well. The first semiconductor layer is formed on the first filling oxide layer, and is doped with impurities having the first conductivity type and electrically connected to the second impurity region. The bit line is electrically connected to the well.

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