-
公开(公告)号：US11967581B2
公开(公告)日：2024-04-23
申请号：US18110446
申请日：2023-02-16
发明人： Jinwoo Park , Unbyoung Kang , Jongho Lee , Teakhoon Lee
IPC分类号： H01L23/16 , H01L23/00 , H01L23/31 , H01L23/367 , H01L25/065
CPC分类号： H01L25/0652 , H01L23/16 , H01L23/3128 , H01L23/3135 , H01L23/3675 , H01L23/562 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2225/06589
摘要： A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.
-
公开(公告)号：US11867757B2
公开(公告)日：2024-01-09
申请号：US17465337
申请日：2021-09-02
发明人： Heejune Lee , Jinwoo Park , Younghyo Park , Eunhye Oh , Sungno Lee , Youngjae Cho , Michael Choi
IPC分类号： G01R31/317 , H03M1/10
CPC分类号： G01R31/31725 , G01R31/31724 , H03M1/1071
摘要： A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.
-
公开(公告)号：US11646064B2
公开(公告)日：2023-05-09
申请号：US17207398
申请日：2021-03-19
发明人： Yongsung Cho , Inho Kang , Taehyo Kim , Jeunghwan Park , Jinwoo Park
CPC分类号： G11C7/1039 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C7/12
摘要： Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
-
公开(公告)号：US20230131700A1
公开(公告)日：2023-04-27
申请号：US18085963
申请日：2022-12-21
发明人： Yongsung Cho , Jinwoo Park , Hyunjun Yoon , Yoonhee Choi
摘要： A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.
-
公开(公告)号：US20220319944A1
公开(公告)日：2022-10-06
申请号：US17573426
申请日：2022-01-11
发明人： Jinwoo Park , Jongho Lee , Yeongkwon Ko , Teakhoon Lee
IPC分类号： H01L23/31 , H01L23/00 , H01L21/56 , H01L25/00 , H01L25/065 , H01L23/498
摘要： A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.
-
公开(公告)号：US20220206062A1
公开(公告)日：2022-06-30
申请号：US17471763
申请日：2021-09-10
发明人： Eunhye Oh , Hyochul Shin , Jinwoo Park , Sungno Lee , Younghyo Park , Yongki Lee , Heejune Lee , Youngjae Cho , Michael Choi
摘要： A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.
-
公开(公告)号：US11264354B2
公开(公告)日：2022-03-01
申请号：US16869988
申请日：2020-05-08
发明人： Jinwoo Park , Jungho Park , Dahye Kim , Minjun Bae
IPC分类号： H01L23/00 , H01L25/065 , H01L23/31
摘要： Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.
-
公开(公告)号：US20220020404A1
公开(公告)日：2022-01-20
申请号：US17207398
申请日：2021-03-19
发明人： Yongsung Cho , Inho Kang , Taehyo Kim , Jeunghwan Park , Jinwoo Park
摘要： Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
-
公开(公告)号：US20210020254A1
公开(公告)日：2021-01-21
申请号：US16804470
申请日：2020-02-28
发明人： Wandong KIM , Jinwoo Park , Seongjin Kim , Sang-wan Nam
摘要： A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.
-
10.发明授权公开(公告)号：US10541033B2
公开(公告)日：2020-01-21
申请号：US15911208
申请日：2018-03-05
发明人： Won-Taeck Jung , Sang-Wan Nam , Jinwoo Park , Jaeyong Jeong
IPC分类号： G11C16/10 , G11C16/20 , G11C16/08 , G11C16/34 , G11C16/04 , H01L27/11582 , H01L27/11524 , H01L27/1157 , H01L27/11556
摘要： A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.
-
-
-
-
-
-
-
-
-
搜索结果
57 条记录 (耗时 0.031 秒)
