公开(公告)号：US20220130786A1

公开(公告)日：2022-04-28

申请号：US17342902

申请日：2021-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung JUNG ,  Jinsu KIM ,  Hyunsuk YANG ,  Kiju LEE ,  Hoyeon JO ,  Ikkyu JIN

IPC: H01L23/00

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.