公开(公告)号：US20230133567A1

公开(公告)日：2023-05-04

申请号：US18149342

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung JUNG ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC: H01L23/00

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

公开(公告)号：US20200152569A1

公开(公告)日：2020-05-14

申请号：US16580156

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Hoyeon Jo ,  Shanghoon Seo ,  Younggwan Ko ,  Sangkyu Lee

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

Abstract: A fan-out semiconductor package includes a frame having a recess portion, and a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the semiconductor chip being disposed in the recess portion. One or more through-grooves are disposed around the recess portion and each penetrate through at least a portion of the frame to each extend in a respective direction along a respective side surface of the semiconductor chip. A metal layer is disposed on side walls of the one or more through-grooves, and an encapsulant covers at least a portion of each of the frame and the semiconductor chip and fills at least a portion of the recess portion. A connection structure is disposed on the frame and the active surface of the semiconductor chip, and includes a redistribution layer electrically connected to the connection pad.

公开(公告)号：US11824033B2

公开(公告)日：2023-11-21

申请号：US18149342

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung Jung ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC: H01L23/00 ,  H01L25/16

CPC classification number: H01L24/20 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/13005 ,  H01L2224/13024 ,  H01L2224/2105 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/24155 ,  H01L2224/24265 ,  H01L2224/2518 ,  H01L2224/25171 ,  H01L2224/73217 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/19041 ,  H01L2924/19104

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

公开(公告)号：US11552038B2

公开(公告)日：2023-01-10

申请号：US17342902

申请日：2021-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung Jung ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.