公开(公告)号：US20240355698A1

公开(公告)日：2024-10-24

申请号：US18762656

申请日：2024-07-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Chi Chu ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Tian Hu

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/58 ,  H01L27/146 ,  H01L31/0203

CPC分类号： H01L23/3192 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/585 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14636 ,  H01L31/0203 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2924/181

摘要： A manufacturing method of a semiconductor package includes: laterally covering a sensing die with an encapsulant, where the encapsulant includes a top surface and a rounded inner edge connected to the top surface, and a top surface of the sensing die is lower than the rounded inner edge of the encapsulant and is smoother than the top surface of the encapsulant; and forming a redistribution structure on the top surface of the encapsulant and the top surface of the sensing die.

公开(公告)号：US20240274567A1

公开(公告)日：2024-08-15

申请号：US18645368

申请日：2024-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hui-Jung Tsai ,  Hung-Jui Kuo ,  Jyun-Siang Peng

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/25 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/50 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/24155 ,  H01L2224/24265 ,  H01L2224/2501 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81355 ,  H01L2224/81815 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161

摘要： A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

公开(公告)号：US20240186283A1

公开(公告)日：2024-06-06

申请号：US18396575

申请日：2023-12-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhih-Yu Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Yung-Chi Chu

IPC分类号： H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC分类号： H01L24/82 ,  H01L23/544 ,  H01L24/02 ,  H01L24/24 ,  H01L24/25 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24155 ,  H01L2224/25171 ,  H01L2224/82106 ,  H01L2224/82132

摘要： An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.

公开(公告)号：US11894336B2

公开(公告)日：2024-02-06

申请号：US17465872

申请日：2021-09-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhih-Yu Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Yung-Chi Chu

IPC分类号： H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC分类号： H01L24/82 ,  H01L23/544 ,  H01L24/02 ,  H01L24/24 ,  H01L24/25 ,  H01L25/0655 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/24155 ,  H01L2224/25171 ,  H01L2224/82106 ,  H01L2224/82132

摘要： An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another.

公开(公告)号：US20230411263A1

公开(公告)日：2023-12-21

申请号：US18332777

申请日：2023-06-12

申请人： STATS ChipPAC Pte. Ltd.

发明人： SooHan PARK ,  KyungEun KIM ,  YouJin SHIN ,  HyeSun KIM

IPC分类号： H01L23/498 ,  H01L25/16 ,  H01L25/03 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L23/49827 ,  H01L25/16 ,  H01L25/03 ,  H01L21/568 ,  H01L21/561 ,  H01L24/24 ,  H01L24/96 ,  H01L24/82 ,  H01L25/50 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/5385 ,  H01L2224/96 ,  H01L2224/24155 ,  H01L2224/24101 ,  H01L2224/82105 ,  H01L2224/2402 ,  H01L2224/82005

摘要： A modular semiconductor device comprises: an encapsulant layer with an encapsulant bottom surface and an encapsulant top surface, wherein the encapsulant layer comprises a component region and an interlayer connection region; wherein the semiconductor component comprises a component conductive pattern exposed from the encapsulant bottom surface; an interlayer connection array disposed within the interlayer connection region, wherein the interlayer connection array comprises one or more conductive vias each extending between the encapsulant bottom surface and the encapsulant top surface; and an interposer layer laminated on the encapsulant layer and having an interposer bottom surface and an interposer top surface, wherein the interposer top surface is in contact with the encapsulant bottom surface; wherein the interposer layer comprises an interposer conductive pattern on the interposer bottom surface, and an interposer interconnection structure electrically coupled to the component conductive pattern, the interposer conductive pattern and the one or more conductive vias.

公开(公告)号：US11824033B2

公开(公告)日：2023-11-21

申请号：US18149342

申请日：2023-01-03

申请人： Samsung Electronics Co., Ltd.

发明人： Gyoyoung Jung ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC分类号： H01L23/00 ,  H01L25/16

CPC分类号： H01L24/20 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/13005 ,  H01L2224/13024 ,  H01L2224/2105 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/24155 ,  H01L2224/24265 ,  H01L2224/2518 ,  H01L2224/25171 ,  H01L2224/73217 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/19041 ,  H01L2924/19104

摘要： A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

公开(公告)号：US20180068937A1

公开(公告)日：2018-03-08

申请号：US15807102

申请日：2017-11-08

申请人： STATS ChipPAC Pte. Ltd.

发明人： Pandi C. Marimuthu ,  Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Won Kyoung Choi

IPC分类号： H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/13 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/14

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81125 ,  H01L2224/81127 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/82 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/92 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/207 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/45099

摘要： A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

公开(公告)号：US09842798B2

公开(公告)日：2017-12-12

申请号：US14135415

申请日：2013-12-19

申请人： STATS ChipPAC, Ltd.

发明人： Pandi C. Marimuthu ,  Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Won Kyoung Choi

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H01L23/13 ,  H01L23/14

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81125 ,  H01L2224/81127 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/82 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/92 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/207 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2224/45099

摘要： A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

公开(公告)号：US20170236788A1

公开(公告)日：2017-08-17

申请号：US15584697

申请日：2017-05-02

申请人： STATS ChipPAC Pte. Ltd.

发明人： Yaojian Lin ,  Jianmin Fang ,  Xia Feng ,  Kang Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/24155 ,  H01L2224/245 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/82986 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/1146

摘要： A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.

公开(公告)号：US09502391B2

公开(公告)日：2016-11-22

申请号：US14404005

申请日：2013-05-09

申请人： NEPES CO., LTD.

发明人： Yong-Tae Kwon ,  Kyung-Hoon Park

IPC分类号： H01L23/02 ,  H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08111 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/32235 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

摘要： Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package includes an insulating substrate including a first through portion and a second through portion; a through wiring which fills the first through portion, and is located to penetrate the insulating substrate; a semiconductor chip which is located in the second through portion, and is electrically connected to the through wiring; a molding member molding the semiconductor chip and the insulating substrate; and a re-wiring pattern layer which is located at a lower side of the insulating substrate, and electrically connects the through wiring and the semiconductor chip.

摘要翻译： 提供一种制造半导体封装的方法，该半导体封装包括具有精度和低工艺缺陷的贯通布线。 半导体封装包括包括第一通孔部分和第二贯通部分的绝缘基板; 贯通配线，其填充所述第一贯通部，并且位于所述绝缘基板上; 半导体芯片，其位于所述第二贯通部分中，并且与所述贯通布线电连接; 模制所述半导体芯片和所述绝缘基板的模制构件; 以及重新布线图案层，其位于绝缘基板的下侧，并且电连接通孔布线和半导体芯片。