公开(公告)号：US20190319042A1

公开(公告)日：2019-10-17

申请号：US16222059

申请日：2018-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Geunwon LIM ,  Hwan LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

公开(公告)号：US20200243559A1

公开(公告)日：2020-07-30

申请号：US16846933

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Geunwon LIM ,  Hwan LEE

IPC: H01L27/11582 ,  H01L27/105 ,  H01L27/11578 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.