公开(公告)号：US20210265390A1

公开(公告)日：2021-08-26

申请号：US17038945

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11519

Abstract: A vertical memory device includes first horizontal gate electrodes disposed on a substrate and spaced apart from each other in a first direction that is substantially perpendicular to an upper surface of the substrate. Each of the first horizontal gate electrodes extends in a second direction that is substantially parallel to the upper surface of the substrate, A vertical channel extends through the first horizontal gate electrodes in the first direction. A charge storage structure is disposed between the vertical channel and each of the first horizontal gate electrodes. A first vertical gate electrode extends through the first horizontal gate electrodes in the first direction. The first vertical gate electrode is electrically insulated from the first horizontal gate electrodes. A first horizontal channel is disposed at a portion of each of the first horizontal gate electrodes adjacent to the first vertical gate electrode.

公开(公告)号：US20210265388A1

公开(公告)日：2021-08-26

申请号：US17035930

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK

IPC: H01L27/11582 ,  H01L27/11565 ,  G11C8/14 ,  H01L23/522 ,  H01L29/423 ,  H01L29/792

Abstract: A vertical memory device includes a plurality of memory blocks having a plurality of horizontal gate electrodes spaced apart from each other in a first direction and extending in a second direction. A plurality of vertical channels extends through the horizontal gate electrodes in the first direction. A plurality of charge storage structures are disposed between the vertical channels and the horizontal gate electrodes. A conductive path extends in a third direction. The plurality of memory blocks are arranged in the third direction and are divided from each other by a first division pattern that extends in the second direction. The plurality of horizontal gate electrodes at each level are connected to the conductive path at a first lateral side in the second direction to form a shared memory block.

公开(公告)号：US20250017013A1

公开(公告)日：2025-01-09

申请号：US18887445

申请日：2024-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H10B43/27 ,  H01L27/06 ,  H10B43/40

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

公开(公告)号：US20240312908A1

公开(公告)日：2024-09-19

申请号：US18484887

申请日：2023-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device includes a substrate including a cell array region and a connection region in a first direction and a stack structure including electrode layers and inter-electrode insulating layers alternately stacked in a second direction, the electrode layers including first electrode layers and second electrode layers alternately stacked, each of the first electrode layers includes a first connection portion in the cell array region and a first front end and a first back end spaced apart from each other in a third direction in the connection region and positioned at the same level as each other, the first front end and the first back end are connected to the first connection portion, the first front end has a first protrusion protruding toward the first back end, and the first protrusions of the first front ends do not overlap the second electrode layers.

公开(公告)号：US20230354597A1

公开(公告)日：2023-11-02

申请号：US18348521

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon LIM ,  Seokcheon BAEK

IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US20230309307A1

公开(公告)日：2023-09-28

申请号：US18080916

申请日：2022-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Miram KWON

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a substrate including a first connection region, a first cell region, a separation region, a second cell region, and a second connection region, which are sequentially disposed in a first direction, a stack structure including electrode layers and insulating layers, which are alternately stacked on the substrate, the electrode layers including upper electrode layers, a first insulating line pattern on the separation region to penetrate the upper electrode layers and extend in a second direction crossing the first direction, second and third insulating line patterns on the separation region to penetrate the first insulating line pattern and the stack structure and to extend in the second direction to divide the stack structure into first and second sub-stack structures, and a remaining stack structure between the second and third insulating line patterns and spaced apart from the first and second sub-stack structures.

公开(公告)号：US20230009932A1

公开(公告)日：2023-01-12

申请号：US17838575

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung LEE ,  Shinhwan KANG ,  Seokcheon BAEK

IPC: H01L23/00 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device including a substrate including first, second, and third regions; a peripheral circuit structure on the substrate and including a peripheral circuit and wiring layers connected to the peripheral circuit; a common source plate on the peripheral circuit structure and extending in a horizontal direction; gate electrodes on the common source plate on the first and second regions, spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, the gate electrodes having a stair shape on the second region; a channel structure extending in the first direction through the gate electrodes on the first region; a first conductive through-via penetrating the common source plate on the third region and electrically connected to the wiring layers; and a dummy insulating pillar adjacent to the first conductive through-via on the third region and connected to an upper surface of the common source plate.

公开(公告)号：US20200243559A1

公开(公告)日：2020-07-30

申请号：US16846933

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Geunwon LIM ,  Hwan LEE

IPC: H01L27/11582 ,  H01L27/105 ,  H01L27/11578 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

公开(公告)号：US20220231038A1

公开(公告)日：2022-07-21

申请号：US17514019

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK ,  Seungjun LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L25/18

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked in a first direction on the first region and each including a pad region having an upper surface exposed upwardly in the second region, channel structures penetrating the gate electrodes and extending in the first direction, separation regions penetrating the gate electrodes and extending in the second direction, contact plugs each penetrating the pad region of each of the gate electrodes and extending in the first direction, a nitride layer disposed in an external side of a lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extending horizontally, and a dummy gate electrode disposed between the lowermost first gate electrode and the nitride layer in the second direction and having a first end spaced apart from the lowermost first gate electrode.

公开(公告)号：US20220059565A1

公开(公告)日：2022-02-24

申请号：US17515981

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon BAEK

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522

Abstract: A three-dimensional semiconductor memory device including: a substrate including a cell array region and a connection region; and an electrode structure extending along a first direction from the cell array region to the connection region and is a plurality of electrodes vertically stacked OD the substrate, each of the electrodes including an electrode portion on the cell array region and a pad portion on the connection region, wherein the electrodes include a first electrode located at a first level from the substrate and a second electrode located at a second level from the substrate, the second level being higher than the first level, and the pad portion of the first electrode is closer to the cell array region than the pad portion of the second electrode.