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    NONVOLATILE MEMORY DEVICE
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220109004A1

    公开(公告)日：2022-04-07

    申请号：US17232500

    申请日：2021-04-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geunwon LIM

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C8/14

    Abstract: A nonvolatile memory device may include a substrate; a first stacked structure on the substrate; a second stacked structure on the first stacked structure; a channel structure including a first portion passing through the first stacked structure and a second portion passing through the second stacked structure; and a filling structure including a first portion passing through the first stacked structure and extending in a first horizontal direction and a second portion passing through the second stacked structure and extending in the first horizontal direction. The upper end of the first portion of the filling structure may be at a same height as the upper end of the first portion of the channel structure.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    2.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190319042A1

    公开(公告)日：2019-10-17

    申请号：US16222059

    申请日：2018-12-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokcheon Baek ,  Geunwon LIM ,  Hwan LEE

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792

    Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210028186A1

    公开(公告)日：2021-01-28

    申请号：US15930867

    申请日：2020-05-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geunwon LIM ,  Yoonhwan SON ,  Junyoung CHOI

    IPC: H01L27/11582 ,  H01L29/51 ,  H01L27/11565 ,  H01L21/28

    Abstract: Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.

    SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION
    5.
    发明公开
    SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION 审中-公开

    公开(公告)号：US20230354597A1

    公开(公告)日：2023-11-02

    申请号：US18348521

    申请日：2023-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geunwon LIM ,  Seokcheon BAEK

    IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

    CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L29/788

    Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    6.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200243559A1

    公开(公告)日：2020-07-30

    申请号：US16846933

    申请日：2020-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokcheon BAEK ,  Geunwon LIM ,  Hwan LEE

    IPC: H01L27/11582 ,  H01L27/105 ,  H01L27/11578 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11565

    Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220123001A1

    公开(公告)日：2022-04-21

    申请号：US17348172

    申请日：2021-06-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangmin KIM ,  Jaehoon SHIN ,  Dongseog EUN ,  Geunwon LIM

    IPC: H01L27/11526 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

    Abstract: A semiconductor device includes a first substrate; devices on the first substrate; a second substrate on the devices; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; channel structures penetrating the gate electrodes, extending in the first direction, and including a channel layer; isolation regions penetrating the gate electrodes and extending in a second direction; a through contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrodes to the devices; a barrier structure spaced apart from the through contact plug and surrounding the through contact plug; and a support structure on the gate electrodes and including support patterns, wherein the support structure has first through regions spaced apart from each other in the second direction on the isolation regions and a second through region in contact with an upper surface of the barrier structure.

    VERTICAL MEMORY DEVICES
    8.
    发明申请
    VERTICAL MEMORY DEVICES 有权

    公开(公告)号：US20210320125A1

    公开(公告)日：2021-10-14

    申请号：US17162408

    申请日：2021-01-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehoon SHIN ,  Kangmin KIM ,  Kyeongjin PARK ,  Seungmin SONG ,  Joongshik SHIN ,  Geunwon LIM

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522

    Abstract: A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210242237A1

    公开(公告)日：2021-08-05

    申请号：US17216867

    申请日：2021-03-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Geunwon LIM ,  SangJun HONG ,  Seokcheon BAEK

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L29/423 ,  H01L21/28

    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

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