公开(公告)号：US20190385915A1

公开(公告)日：2019-12-19

申请号：US16249353

申请日：2019-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin PARK ,  Kyoung Hwan YEO ,  Jong Mil YOUN ,  Hwasung RHEE

IPC: H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate including at least a first region, first active patterns and a first dummy pattern which vertically protrude from the first region, a device isolation layer filling a first trench, a second trench and a third trench of the substrate, and a gate electrode intersecting the first active patterns. The first trench defines the first active patterns on the first region, the second trench defines a first sidewall of the first region, and the third trench defines a second sidewall of the first region, which is opposite to the first sidewall. A sidewall of the first dummy pattern is aligned with the second sidewall of the first region, and a level of a top of the second sidewall of the first region is higher than a level of a top of the first sidewall of the first region.

公开(公告)号：US20190067287A1

公开(公告)日：2019-02-28

申请号：US16176179

申请日：2018-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min YOO ,  Sangyoon KIM ,  Woosik KIM ,  Jongmil YOUN ,  Hwasung RHEE ,  Heedon JEONG

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.