公开(公告)号：US20250157518A1

公开(公告)日：2025-05-15

申请号：US18891518

申请日：2024-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwayeong Lee ,  Seulji Song

IPC: G11C11/22 ,  H10B53/30

Abstract: An operating method of a memory device includes, during a write operation, in a first time period, pre-charging a bit line connected to a memory cell with a ground voltage, during the write operation, in a second time period, applying a word line driving voltage to a word line corresponding to the bit line, in the second time period, applying a plate line driving voltage to a plate line connected to the memory cell, and in the second time period, maintaining a voltage applied to the bit line at the ground voltage.

公开(公告)号：US20250015135A1

公开(公告)日：2025-01-09

申请号：US18732958

申请日：2024-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayeong Lee ,  Seulji Song

IPC: H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H10B12/00

Abstract: A vertical channel transistor includes a substrate having a bit line thereon, and a vertical channel layer including a first metal oxide, on the bit line. A lower insertion layer is provided, which extends between the bit line and a first end of the channel layer, and includes a second metal oxide having a greater bonding energy relative to the first metal oxide. A lower source/drain region is provided, which extends between the first end of the channel layer and the lower insertion layer, and includes a first metal dopant that is a reduced form of the first metal oxide. An upper source/drain region is provided, which is electrically connected to a second end of the channel layer, and includes the first metal dopant. An insulated gate line is provided on the channel layer.

公开(公告)号：US20250063738A1

公开(公告)日：2025-02-20

申请号：US18801958

申请日：2024-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seulji Song ,  Hwayeong Lee

IPC: H10B53/30

Abstract: A semiconductor memory device includes an active portion, a pad insulating layer on the active portion and including a pad through hole, a landing pad in the pad through hole and electrically connected to the active portion, and the landing pad including a protrusion protruding towards an upper portion of the pad insulating layer, a lower conductive layer on the pad insulating layer and bordering a side surface of the protrusion of the landing pad, a lower electrode on the landing pad and electrically connected to the landing pad, a ferroelectric layer on the lower conductive layer and bordering the lower electrode, an upper electrode bordering the ferroelectric layer, an electrode insulating layer on the upper electrode, a plate line on the electrode insulating layer and the upper electrode and electrically connected to the upper electrode, wherein the plate line is electrically connected to the lower conductive layer through a through via.

公开(公告)号：US20250054532A1

公开(公告)日：2025-02-13

申请号：US18797698

申请日：2024-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayeong Lee ,  Seulji Song

IPC: G11C11/22

Abstract: A memory device including a ferroelectric cell capacitor, and an operating method thereof. For example, an operating method of a memory device, according to some embodiments, may include pre-charging a bit line to a pre-charge voltage, the bit line connected to a ferroelectric cell capacitor to be written to, writing data into the ferroelectric cell capacitor by adjusting a level of a voltage applied to a bit line and a word line corresponding to the ferroelectric cell capacitor, and deactivating the word line, wherein a voltage applied to a plate line connected to the ferroelectric cell capacitor is maintained at a ground voltage during the writing of the data into the ferroelectric cell capacitor.

公开(公告)号：US20250157934A1

公开(公告)日：2025-05-15

申请号：US18918467

申请日：2024-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bang ,  Seulji Song ,  Hwayeong Lee

IPC: H01L23/532 ,  H10B12/00

Abstract: A semiconductor device includes a bit line above a substrate and extending in a first horizontal direction, a word line at a higher vertical level than the bit line and extending in a second horizontal direction crossing the first horizontal direction, a fluorine-containing insulating layer spaced apart from the word line and extending in the second horizontal direction, and a channel layer between the word line and the fluorine-containing insulating layer, the channel layer including a first side surface and a second side surface opposite to the first side surface. The first side surface faces the word line, and the channel layer includes an oxide semiconductor and fluorine.