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    Semiconductor devices with circuit and external dummy areas
    1.
    发明授权
    Semiconductor devices with circuit and external dummy areas 有权

    公开(公告)号：US11410994B2

    公开(公告)日：2022-08-09

    申请号：US17024044

    申请日：2020-09-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seonah Nam ,  Byungju Kang ,  Byungsung Kim ,  Hyelim Kim ,  Sungho Park ,  Yubo Qian

    IPC: H01L27/088 ,  H01L23/538 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/02 ,  H01L29/775 ,  H01L29/78

    Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

    Integrated circuits and semiconductor device including standard cell
    3.
    发明授权
    Integrated circuits and semiconductor device including standard cell 有权

    公开(公告)号：US10943923B2

    公开(公告)日：2021-03-09

    申请号：US16574339

    申请日：2019-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo Jeong ,  Jiwook Kwon ,  Sutae Kim ,  Hyelim Kim

    IPC: H01L27/118 ,  H01L27/02

    Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

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