公开(公告)号：US20220149821A1

公开(公告)日：2022-05-12

申请号：US17385182

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Chul HWANG ,  Min Su KIM

IPC: H03K3/037

Abstract: A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.