公开(公告)号：US10600346B2

公开(公告)日：2020-03-24

申请号：US15454062

申请日：2017-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong Ho Kim ,  Young Min Choi ,  Dong Hoon Baek ,  Jae Youl Lee ,  Hyun Wook Lim

IPC: G09G3/36 ,  G09G3/00 ,  G09G3/20

Abstract: A display driving device includes a timing controller configured to generate test data having a predetermined periodicity, and a source driver configured to drive source lines of a display panel using the test data, determine that a bit error has been generated when aperiodicity appears in the test data, and measure a bit error rate (BER) based on the bit error.

公开(公告)号：US10170033B2

公开(公告)日：2019-01-01

申请号：US15358906

申请日：2016-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwi Sung Yoo ,  Dong Hoon Baek ,  Dong Myung Lee ,  Hyun Wook Lim ,  Eun Young Jin ,  Jae Youl Lee

IPC: G09G3/20

Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

公开(公告)号：US20170148377A1

公开(公告)日：2017-05-25

申请号：US15358906

申请日：2016-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWI SUNG YOO ,  Dong-Hoon Baek ,  Dong Myung Lee ,  Hyun Wook Lim ,  Eun Young Jin ,  Jae Youl Lee

IPC: G09G3/20

CPC classification number: G09G3/2096 ,  G09G3/2092 ,  G09G2310/0221 ,  G09G2370/08 ,  G09G2370/10

Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

公开(公告)号：US11146378B2

公开(公告)日：2021-10-12

申请号：US16889077

申请日：2020-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Kim ,  Jung-Hoon Chun ,  Jae Youl Lee ,  Hyun Wook Lim

IPC: H04B1/10 ,  H04L7/00 ,  H03G3/30 ,  H03K3/037 ,  H03K19/20

Abstract: A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.

公开(公告)号：US10698852B2

公开(公告)日：2020-06-30

申请号：US15941607

申请日：2018-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin Kim ,  Hyun Wook Lim ,  Seong Young Ryu ,  Soo Joo Lee

IPC: G06F13/40 ,  H03K19/0175 ,  G09G3/20 ,  G09G5/00

Abstract: A termination circuit is provided. The termination device includes terminals configured to receive a corresponding signal; unit circuits respectively connected to the terminals, the unit circuits each including a unit resistor and a unit switch element connected to each other in series; common mode capacitors; first switch elements respectively connected between each of the unit circuits and a first corresponding common mode capacitor of common mode capacitors, each of the first switch elements being configured to turn on when the corresponding signal is received in a first mode; and second switch elements respectively connected between each of the unit circuits and a second corresponding common mode capacitor of the common mode capacitors, the second switch elements being configured to turn on when the corresponding signal is received in a second mode different from the first mode.