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公开(公告)号：US11146378B2
公开(公告)日：2021-10-12
申请号：US16889077
申请日：2020-06-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-Jin Kim , Jung-Hoon Chun , Jae Youl Lee , Hyun Wook Lim
Abstract: A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.
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2.发明授权Phase locked loop for preventing harmonic lock, method of operating the same, and devices including the same 有权用于防止谐波锁定的锁相环，其操作方法和包括其的装置公开(公告)号：US09525545B2
公开(公告)日：2016-12-20
申请号：US14182029
申请日：2014-02-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woon Taek Oh , Jin Ho Kim , Tae Jin Kim , Jae Youl Lee , Young Hwan Chang
CPC classification number: H04L7/0331 , G09G3/20 , G09G5/02 , G09G2310/0267 , G09G2310/027 , G11C7/1096 , G11C7/222 , H03L7/095 , H04L7/033
Abstract: A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.
Abstract translation: 锁相环包括压控振荡器，其包括被配置为分别产生具有不同相位的多个时钟信号的多个延迟单元和被配置为检测压控振荡器中的谐波锁定并且响应地产生复位信号的谐波锁定检测器 。 多个延迟单元中除第一延迟单元之外的延迟单元的剩余的单元响应于复位信号被复位。
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公开(公告)号：US10580118B2
公开(公告)日：2020-03-03
申请号：US15968963
申请日：2018-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwa Hyun Cho , Yoon Ho Ko , Tae Kon Yu , Jae Youl Lee
Abstract: A display driver includes an interface circuit configured to receive an input image of a virtual reality (VR) experience from at least one of an application processor (AP) and a graphics processing unit (GPU); a coordinate correction circuit configured to generate corrected coordinates by adjusting input coordinates of pixels included in the input image; and an image generation circuit configured to generate an output image by distorting the input image using the corrected coordinates.
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公开(公告)号：US20190156466A1
公开(公告)日：2019-05-23
申请号：US15968963
申请日：2018-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwa Hyun Cho , Yoon Ho Ko , Tae Kon Yu , Jae Youl Lee
Abstract: A display driver includes an interface circuit configured to receive an input image of a virtual reality (VR) experience from at least one of an application processor (AP) and a graphics processing unit (GPU); a coordinate correction circuit configured to generate corrected coordinates by adjusting input coordinates of pixels included in the input image; and an image generation circuit configured to generate an output image by distorting the input image using the corrected coordinates.
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公开(公告)号：US10170033B2
公开(公告)日：2019-01-01
申请号：US15358906
申请日：2016-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwi Sung Yoo , Dong Hoon Baek , Dong Myung Lee , Hyun Wook Lim , Eun Young Jin , Jae Youl Lee
IPC: G09G3/20
Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.
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Patent Agency Ranking
公开(公告)号：US10600346B2
公开(公告)日：2020-03-24
申请号：US15454062
申请日：2017-03-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyong Ho Kim , Young Min Choi , Dong Hoon Baek , Jae Youl Lee , Hyun Wook Lim
Abstract: A display driving device includes a timing controller configured to generate test data having a predetermined periodicity, and a source driver configured to drive source lines of a display panel using the test data, determine that a bit error has been generated when aperiodicity appears in the test data, and measure a bit error rate (BER) based on the bit error.
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公开(公告)号：US09432028B2
公开(公告)日：2016-08-30
申请号：US14716106
申请日：2015-05-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae Jin Kim , Chang Hoon Baek , Sang Kyu Lee , Jae Youl Lee
CPC classification number: H03L7/0807 , H03L1/00 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/093 , H03L7/0992 , H03L7/0995 , H03L7/113 , H03L7/187 , H03L2207/06 , H03L2207/50
Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.
Abstract translation: 一种时钟数据恢复电路，包括：数字相位检测器和解串器，被配置为使用恢复时钟信号对串行数据进行采样，以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器，其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器，被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。
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8.发明申请Phase Locked Loop for Preventing Harmonic Lock, Method of Operating the Same, and Devices Including the Same 有权用于防止谐波锁定的锁相环，其操作方法及包括它的设备公开(公告)号：US20140240371A1
公开(公告)日：2014-08-28
申请号：US14182029
申请日：2014-02-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woon Taek Oh , Jin Ho Kim , Tae Jin Kim , Jae Youl Lee , Young Hwan Chang
CPC classification number: H04L7/0331 , G09G3/20 , G09G5/02 , G09G2310/0267 , G09G2310/027 , G11C7/1096 , G11C7/222 , H03L7/095 , H04L7/033
Abstract: A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.
Abstract translation: 锁相环包括压控振荡器，其包括被配置为分别产生具有不同相位的多个时钟信号的多个延迟单元和被配置为检测压控振荡器中的谐波锁定并且响应地产生复位信号的谐波锁定检测器 。 多个延迟单元中除第一延迟单元之外的延迟单元的剩余的单元响应于复位信号被复位。
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公开(公告)号：US10510281B2
公开(公告)日：2019-12-17
申请号：US15646227
申请日：2017-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho Seok Shin , Un Ki Park , Se Whan Na , Jae Youl Lee , Jong Hyuk Lee
Abstract: An image processing apparatus includes: an analyzer configured to calculate color characteristics by input pixel data, and determine whether the pixel data is achromatic based on the color characteristics; a first renderer configured to perform a first rendering on the pixel data in response to determining that the pixel data is not achromatic; and a second renderer configured to perform a second rendering on the pixel data in response to determining that the pixel data is achromatic.
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公开(公告)号：US20170148377A1
公开(公告)日：2017-05-25
申请号：US15358906
申请日：2016-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KWI SUNG YOO , Dong-Hoon Baek , Dong Myung Lee , Hyun Wook Lim , Eun Young Jin , Jae Youl Lee
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G3/2092 , G09G2310/0221 , G09G2370/08 , G09G2370/10
Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.
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