Signal receiving device and method of recovering clock and calibration of the device

    公开(公告)号:US11146378B2

    公开(公告)日:2021-10-12

    申请号:US16889077

    申请日:2020-06-01

    Abstract: A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.

    Display driver and mobile electronic device

    公开(公告)号:US10580118B2

    公开(公告)日:2020-03-03

    申请号:US15968963

    申请日:2018-05-02

    Abstract: A display driver includes an interface circuit configured to receive an input image of a virtual reality (VR) experience from at least one of an application processor (AP) and a graphics processing unit (GPU); a coordinate correction circuit configured to generate corrected coordinates by adjusting input coordinates of pixels included in the input image; and an image generation circuit configured to generate an output image by distorting the input image using the corrected coordinates.

    DISPLAY DRIVER AND MOBILE ELECTRONIC DEVICE
    4.
    发明申请

    公开(公告)号:US20190156466A1

    公开(公告)日:2019-05-23

    申请号:US15968963

    申请日:2018-05-02

    Abstract: A display driver includes an interface circuit configured to receive an input image of a virtual reality (VR) experience from at least one of an application processor (AP) and a graphics processing unit (GPU); a coordinate correction circuit configured to generate corrected coordinates by adjusting input coordinates of pixels included in the input image; and an image generation circuit configured to generate an output image by distorting the input image using the corrected coordinates.

    Clock data recovery circuit and a method of operating the same
    7.
    发明授权
    Clock data recovery circuit and a method of operating the same 有权
    时钟数据恢复电路及其操作方法

    公开(公告)号:US09432028B2

    公开(公告)日:2016-08-30

    申请号:US14716106

    申请日:2015-05-19

    Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.

    Abstract translation: 一种时钟数据恢复电路,包括:数字相位检测器和解串器,被配置为使用恢复时钟信号对串行数据进行采样,以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器,其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器,被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。

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