公开(公告)号：US10957380B2

公开(公告)日：2021-03-23

申请号：US16369034

申请日：2019-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-sung Shin ,  Dae-Jeong Kim ,  Ik-Joon Choi

IPC: G11C11/40 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06 ,  G11C17/18 ,  G11C17/16

Abstract: According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.