公开(公告)号：US20250004381A1

公开(公告)日：2025-01-02

申请号：US18432182

申请日：2024-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungju Ryu ,  Dokyeong Kwon ,  Sangjin Kim ,  Changmin Park

IPC: G03F7/38

Abstract: Methods of forming a photoresist pattern are provided. A photoresist layer may be formed on a substrate. An exposure process may be performed on the photoresist layer. A post exposure baking (PEB) process may be performed on the photoresist layer with a temperature gradient in the photoresist layer in a vertical direction substantially perpendicular to an upper surface of the substrate. A development process may be performed on the photoresist layer.

公开(公告)号：US20240355757A1

公开(公告)日：2024-10-24

申请号：US18408215

申请日：2024-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyun Kim ,  Sangjin Kim ,  Jaesuk Park ,  Yigwon Kim ,  Changmin Park ,  Hyungju Ryu

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: The present disclosure relates to semiconductor devices and their fabrication methods. An example semiconductor device comprises a substrate including a logic cell region and a key region, a dummy active pattern on the key region, and a key pattern in the dummy active pattern. The key pattern includes a key cell that is recessed at an upper portion of the substrate. The key cell includes a bottom surface lower than a top surface of the dummy active pattern, and a plurality of inner lateral surfaces that surround the bottom surface. The inner lateral surfaces include a first inner lateral surface and a second inner lateral surface opposite to the first inner lateral surface. A ratio of a silicon atom surface density of the second inner lateral surface to a silicon atom surface density of the first inner lateral surface is in a range of about 0.9 to about 1.1.