公开(公告)号：US20250101145A1

公开(公告)日：2025-03-27

申请号：US18824037

申请日：2024-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyeon An ,  Yeonsik Jung ,  Yemin Park ,  Jeehyun Hong ,  Youngseog Kang ,  Changmin Park ,  Kwangsub Yoon ,  Jisun Lee

IPC: C08F8/32 ,  C08F293/00 ,  H01L21/027 ,  H01L21/308

Abstract: A block copolymer is described, such as one including a first polymer block and a second polymer block that have different structures, wherein the first polymer block includes a first unit derived from an acrylic acid ester, and the second polymer block includes an inorganic material-containing random block, in which a second unit including an inorganic material-containing group and a third unit that is devoid of an inorganic material-containing group are connected to each other to provide a concentration gradient. Also described are methods of manufacturing an integrated circuit device that include forming, on a feature layer, a block copolymer layer including the block copolymer as set forth above; phase-separating the block copolymer layer to form a structure that includes a plurality of first domains that each include the first polymer block, and at least one second domain including the second polymer block; removing the plurality of first domains; and etching the feature layer using the at least one second domain as an etch mask.

公开(公告)号：US11658073B2

公开(公告)日：2023-05-23

申请号：US17405134

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongchan Shin ,  Changmin Park

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/8234 ,  H01L21/3086 ,  H01L27/088

Abstract: A semiconductor device includes; a substrate including a first region and a second region adjacent to the first region in a first direction, a pair of active patterns adjacently disposed on the substrate, wherein the pair of active patterns includes a first active pattern extending in the first direction and a second active pattern extending in parallel with the first active pattern, a first gate electrode on the first region and extending in a second direction that intersect the first direction across the first active pattern and the second active pattern, and a second gate electrode on the second region and extending in the second direction across the first active pattern and the second active pattern. A width of the first active pattern is greater on the first region than on the second region, a width of the second active pattern is greater on the first region than on the second region, and an interval between the first active pattern and the second active pattern is constant from the first region to the second region.

公开(公告)号：US20220216150A1

公开(公告)日：2022-07-07

申请号：US17409069

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchan Shin ,  Woojeong Shin ,  Changmin Park ,  Noyoung Chung

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a logic cell on a substrate and a first metal layer on the logic cell. The first metal layer includes first and second power lines that extend in a first direction, and first, second, and third lower interconnection lines, which are respectively disposed on first, second, and third interconnection tracks defined between the first and second power lines that extend in the first direction parallel to each other. The first lower interconnection line includes first and second interconnection lines spaced apart from each other by a first distance, and the third lower interconnection line includes third and fourth interconnection lines spaced apart from each other by a second distance. The first and third interconnection lines have first and second ends, respectively, which face the second and fourth interconnection lines, respectively, and have different curvatures.

公开(公告)号：US20250004381A1

公开(公告)日：2025-01-02

申请号：US18432182

申请日：2024-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungju Ryu ,  Dokyeong Kwon ,  Sangjin Kim ,  Changmin Park

IPC: G03F7/38

Abstract: Methods of forming a photoresist pattern are provided. A photoresist layer may be formed on a substrate. An exposure process may be performed on the photoresist layer. A post exposure baking (PEB) process may be performed on the photoresist layer with a temperature gradient in the photoresist layer in a vertical direction substantially perpendicular to an upper surface of the substrate. A development process may be performed on the photoresist layer.

公开(公告)号：US20240355757A1

公开(公告)日：2024-10-24

申请号：US18408215

申请日：2024-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyun Kim ,  Sangjin Kim ,  Jaesuk Park ,  Yigwon Kim ,  Changmin Park ,  Hyungju Ryu

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: The present disclosure relates to semiconductor devices and their fabrication methods. An example semiconductor device comprises a substrate including a logic cell region and a key region, a dummy active pattern on the key region, and a key pattern in the dummy active pattern. The key pattern includes a key cell that is recessed at an upper portion of the substrate. The key cell includes a bottom surface lower than a top surface of the dummy active pattern, and a plurality of inner lateral surfaces that surround the bottom surface. The inner lateral surfaces include a first inner lateral surface and a second inner lateral surface opposite to the first inner lateral surface. A ratio of a silicon atom surface density of the second inner lateral surface to a silicon atom surface density of the first inner lateral surface is in a range of about 0.9 to about 1.1.