公开(公告)号：US20180367154A1

公开(公告)日：2018-12-20

申请号：US15802601

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangyeop CHOO ,  Wonsik YU ,  Wooseok KIM ,  Jihyun KIM ,  Taeik KIM ,  Hyunik KIM

IPC: H03L7/107 ,  H03L7/099 ,  H03L7/091 ,  H03L7/18 ,  H03L7/087 ,  H03L7/199

CPC classification number: H03L7/1072 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/199

Abstract: A digital phase locked loop circuit includes a phase frequency detector, a bandwidth calibrator, a digital loop filter, and a digital controlled oscillator. The phase frequency detector generates a first detection value and a second detection value of which each is associated with order between a phase of a reference signal and a phase of a fed-back signal. The bandwidth calibrator amplifies a signal level of the second detection value by a gain value to generate an amplified detection value, and adjusts the gain value based on the first detection value. The digital loop filter generates a digital code based on the amplified detection value. The digital controlled oscillator generates an output signal having a frequency which corresponds to the digital code. The fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.