公开(公告)号：US20230082930A1

公开(公告)日：2023-03-16

申请号：US17943932

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dokyung LIM ,  Sounghun SHIN ,  Wooseok KIM ,  Wonsik YU ,  Chanyoung JEONG

IPC: H04L7/033 ,  H04L43/087

Abstract: A monitoring circuit for a high frequency signal includes: a phase locked loop configured to generate a divided output signal with respect to an input signal based on a plurality of dividers; a plurality of dividing monitoring circuits configured to receive dividing input signals and dividing output signals respectively corresponding to the plurality of dividers, and output dividing error signals; and a jitter monitoring circuit configured to output a jitter error signal.

公开(公告)号：US20240120927A1

公开(公告)日：2024-04-11

申请号：US18142939

申请日：2023-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jusung LEE ,  Wonsik YU ,  Youngwoo JO ,  Wooseok KIM

IPC: H03L7/091 ,  H03L7/089

CPC classification number: H03L7/091 ,  H03L7/089

Abstract: A phase-locked loop device and its operating method are provided. The phase-locked loop device includes a voltage controlled oscillator configured to generate an output clock signal, a divider configured to divide the output clock signal into first and second phase division signals having a constant phase difference, a sampling phase frequency detector configured to sample a sampling voltage based on the first phase division signal and output any one of the sampling voltage, a first supply voltage, and a second supply voltage based on the second phase division signal, a transconductance circuit configured to output a conversion current based on a hold voltage, and a loop filter configured to generate a voltage control signal based on the conversion current and output the voltage control signal to the voltage controlled oscillator.

公开(公告)号：US20230145187A1

公开(公告)日：2023-05-11

申请号：US17980728

申请日：2022-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dokyung LIM ,  Wooseok KIM ,  Wonsik YU ,  Chanyoung JEONG

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit device includes a substrate, and a unit cell on the substrate. The unit cell defines a unit cell area including at least two discrete devices. The unit cell includes a routing layer configured to route a signal and a voltage to the at least two discrete devices, the routing layer including a signal line and a voltage line extending in a first direction, and the signal line and the voltage line spaced apart from each other in a second direction, and a metal line stack including metal lines stacked between the unit cell area and the routing layer in the first direction. A plurality of contact vias are each configured to connect at least two adjacent ones of the signal line, the voltage line, the metal lines and the at least two discrete devices, in a third direction.

公开(公告)号：US20180367154A1

公开(公告)日：2018-12-20

申请号：US15802601

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangyeop CHOO ,  Wonsik YU ,  Wooseok KIM ,  Jihyun KIM ,  Taeik KIM ,  Hyunik KIM

IPC: H03L7/107 ,  H03L7/099 ,  H03L7/091 ,  H03L7/18 ,  H03L7/087 ,  H03L7/199

CPC classification number: H03L7/1072 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/199

Abstract: A digital phase locked loop circuit includes a phase frequency detector, a bandwidth calibrator, a digital loop filter, and a digital controlled oscillator. The phase frequency detector generates a first detection value and a second detection value of which each is associated with order between a phase of a reference signal and a phase of a fed-back signal. The bandwidth calibrator amplifies a signal level of the second detection value by a gain value to generate an amplified detection value, and adjusts the gain value based on the first detection value. The digital loop filter generates a digital code based on the amplified detection value. The digital controlled oscillator generates an output signal having a frequency which corresponds to the digital code. The fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.