公开(公告)号：US11380706B2

公开(公告)日：2022-07-05

申请号：US16936888

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong Park ,  Hyunseok Na ,  Jaeduk Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

公开(公告)号：US11974434B2

公开(公告)日：2024-04-30

申请号：US17824821

申请日：2022-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong Park ,  Hyunseok Na ,  Jaeduk Lee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.