公开(公告)号：US20210272623A1

公开(公告)日：2021-09-02

申请号：US17322227

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20190371391A1

公开(公告)日：2019-12-05

申请号：US16228518

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20210005247A1

公开(公告)日：2021-01-07

申请号：US17024259

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20190146870A1

公开(公告)日：2019-05-16

申请号：US16023835

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn CHA ,  Myeong-O KIM ,  In-Woo JUN

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G06F3/06

Abstract: Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.

公开(公告)号：US20200168269A1

公开(公告)日：2020-05-28

申请号：US16779194

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.