公开(公告)号：US20190371391A1

公开(公告)日：2019-12-05

申请号：US16228518

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20210005247A1

公开(公告)日：2021-01-07

申请号：US17024259

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20200044669A1

公开(公告)日：2020-02-06

申请号：US16599648

申请日：2019-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn CHA ,  Ye-Sin RYU ,  Young-Sik KIM ,  Su-Yeon DOO

IPC: H03M13/29 ,  H03M13/09

Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

公开(公告)号：US20200168269A1

公开(公告)日：2020-05-28

申请号：US16779194

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20210272623A1

公开(公告)日：2021-09-02

申请号：US17322227

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hyun-Gi KIM ,  Hoon SIN ,  Ye-Sin RYU ,  In-Woo JUN

IPC: G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20190027230A1

公开(公告)日：2019-01-24

申请号：US16140673

申请日：2018-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ye-Sin RYU ,  Sang-Uhn CHA

IPC: G11C29/42 ,  G11C29/44 ,  G06F11/07 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array including a plurality of dynamic memory cells, an ECC engine configured to correct at least one error in a read data from the memory cell array, and a test circuit which performs a test on the memory cell array in a test mode of the semiconductor memory device by writing a test pattern data in the memory cell array and by reading, from the memory cell array, test result data corresponding to the test pattern data. When the test result data includes at least one error bit, the test circuit subtracts a second number from a first number of the at least one error bit and is configured to output the subtracted result to an outside of the semiconductor memory device. The second number corresponds to a number of error bits that the ECC engine is capable of correcting.

公开(公告)号：US20180060194A1

公开(公告)日：2018-03-01

申请号：US15596540

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ye-Sin RYU ,  Jong-Wook PARK ,  Youn-Hyung KANG

IPC: G06F11/16 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1666 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1048 ,  G06F11/108 ,  G06F2201/805 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method of operating a semiconductor memory device including a memory cell array and an error correction code (ECC) engine, wherein the memory cell array includes a plurality of memory cells and the ECC engine is configured to perform an error correction operation on data of the memory cell array, may include storing, in a nonvolatile storage, a mapping information indicating physical addresses of normal cells to swap with a portion of fail cells when a first unit of memory cells includes a number of the fail cells exceeding an error correction capability of the ECC engine. The first unit of memory cells of the memory cells may be accessed based on a logical address. The method may include performing a memory operation on the memory cell array selectively based on the mapping information.