公开(公告)号：US20250149080A1

公开(公告)日：2025-05-08

申请号：US18784796

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee Cho ,  Incheol Nam ,  Kyuchang Kang ,  Sangyun Kim ,  Sunyoung Kim ,  Jongwook Park ,  Hoseok Lee ,  Kangsub Jeong

IPC: G11C11/4091 ,  G11C11/4094

Abstract: A memory device includes a memory cell array, a sense amplifier, a voltage generation circuit and a control circuit. The memory cell array includes a plurality of bit lines to which a plurality of memory cells are connected, and a shielding bit line arranged between the plurality of bit lines and on lower portions of the plurality of bit lines. The sense amplifier is configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells. The voltage generation circuit is configured to generate a bit line precharge voltage and an internal power voltage based on a power voltage of the memory device. The control circuit is configured to selectively provide the shielding bit line with the bit line precharge voltage or the internal power voltage.