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    Semiconductor memory devices including sense amplifier adjusted based on error information
    1.
    发明授权
    Semiconductor memory devices including sense amplifier adjusted based on error information 有权

    公开(公告)号：US11501823B2

    公开(公告)日：2022-11-15

    申请号：US16812850

    申请日：2020-03-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangyun Kim ,  Younghun Seo ,  Hyejung Kwon ,  Myungkyu Lee ,  Sunghye Cho

    IPC: G11C11/4091 ,  G11C11/56 ,  G11C11/4074 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME
    2.
    发明申请
    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME 有权

    公开(公告)号：US20210225425A1

    公开(公告)日：2021-07-22

    申请号：US17038488

    申请日：2020-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/406 ,  G11C5/06

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

    Word line driver circuits for memory devices and methods of operating same
    3.
    发明授权
    Word line driver circuits for memory devices and methods of operating same 有权

    公开(公告)号：US12198749B2

    公开(公告)日：2025-01-14

    申请号：US17819289

    申请日：2022-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

    MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME
    4.
    发明公开
    MEMORY CORE CIRCUITS HAVING CELL-ON-PERIPHERY STRUCTURES AND MEMORY DEVICES INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240096403A1

    公开(公告)日：2024-03-21

    申请号：US18325307

    申请日：2023-05-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoseok Lee ,  Younghun Seo ,  Kangsub Jeong ,  Sangyun Kim ,  Dongil Lee

    IPC: G11C11/4091 ,  G11C11/408

    CPC classification number: G11C11/4091 ,  G11C11/4085 ,  G11C11/4087

    Abstract: A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.

    Memory device and an operating method thereof
    6.
    发明授权
    Memory device and an operating method thereof 有权

    公开(公告)号：US11551729B2

    公开(公告)日：2023-01-10

    申请号：US17215914

    申请日：2021-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangyun Kim ,  Kyungryun Kim ,  Junghwan Park ,  Yeonkyu Choi

    IPC: G11C11/34 ,  G11C5/14 ,  G11C7/22 ,  G11C7/06

    Abstract: A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.

    MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES
    7.
    发明申请
    MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES 有权

    公开(公告)号：US20250149080A1

    公开(公告)日：2025-05-08

    申请号：US18784796

    申请日：2024-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junhee Cho ,  Incheol Nam ,  Kyuchang Kang ,  Sangyun Kim ,  Sunyoung Kim ,  Jongwook Park ,  Hoseok Lee ,  Kangsub Jeong

    IPC: G11C11/4091 ,  G11C11/4094

    Abstract: A memory device includes a memory cell array, a sense amplifier, a voltage generation circuit and a control circuit. The memory cell array includes a plurality of bit lines to which a plurality of memory cells are connected, and a shielding bit line arranged between the plurality of bit lines and on lower portions of the plurality of bit lines. The sense amplifier is configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells. The voltage generation circuit is configured to generate a bit line precharge voltage and an internal power voltage based on a power voltage of the memory device. The control circuit is configured to selectively provide the shielding bit line with the bit line precharge voltage or the internal power voltage.

    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME
    8.
    发明申请
    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME 有权

    公开(公告)号：US20220383932A1

    公开(公告)日：2022-12-01

    申请号：US17819289

    申请日：2022-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

    Word line driver circuits for memory devices and methods of operating same
    10.
    发明授权
    Word line driver circuits for memory devices and methods of operating same 有权

    公开(公告)号：US11450376B2

    公开(公告)日：2022-09-20

    申请号：US17038488

    申请日：2020-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/406 ,  G11C11/4074

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

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