公开(公告)号：US20250149080A1

公开(公告)日：2025-05-08

申请号：US18784796

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee Cho ,  Incheol Nam ,  Kyuchang Kang ,  Sangyun Kim ,  Sunyoung Kim ,  Jongwook Park ,  Hoseok Lee ,  Kangsub Jeong

IPC: G11C11/4091 ,  G11C11/4094

Abstract: A memory device includes a memory cell array, a sense amplifier, a voltage generation circuit and a control circuit. The memory cell array includes a plurality of bit lines to which a plurality of memory cells are connected, and a shielding bit line arranged between the plurality of bit lines and on lower portions of the plurality of bit lines. The sense amplifier is configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells. The voltage generation circuit is configured to generate a bit line precharge voltage and an internal power voltage based on a power voltage of the memory device. The control circuit is configured to selectively provide the shielding bit line with the bit line precharge voltage or the internal power voltage.

公开(公告)号：US20240096403A1

公开(公告)日：2024-03-21

申请号：US18325307

申请日：2023-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok Lee ,  Younghun Seo ,  Kangsub Jeong ,  Sangyun Kim ,  Dongil Lee

IPC: G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C11/4085 ,  G11C11/4087

Abstract: A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.