公开(公告)号：US20210242125A1

公开(公告)日：2021-08-05

申请号：US16947693

申请日：2020-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG HO DO

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Integrated circuit devices including standard cells are provided. The integrated devices may include a lower transistor region and an upper transistor region. The lower transistor region may include a lower active region, lower source/drain regions, and lower gate structures arranged alternately with the lower source/drain regions. The upper transistor region may include an upper active region, upper source/drain regions, and upper gate structures arranged alternately with the upper source/drain regions. The upper gate structures may include a first upper gate structure. The integrated devices may also include an input wire, an input via electrically connecting the input wire to the first upper gate structure, and a routing wire electrically connecting a pair of the lower source/drain regions or a pair of the upper source/drain regions. An upper surface of the routing wire may be closer to the substrate than an upper surface of the input wire.

公开(公告)号：US20200295146A1

公开(公告)日：2020-09-17

申请号：US16520717

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG HO DO ,  Seung Hyun Song

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L27/02

Abstract: Integrated circuit devices may include active regions spaced apart from each other in a direction. The active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions. The first pair of active regions may be spaced apart from each other by a first distance in the direction, the second pair of active regions may be spaced apart from each other by the first distance in the direction, and the third pair of active regions may be spaced apart from each other by the first distance in the direction. The second pair of active regions may be spaced apart from the first pair of active regions and the third pair of active regions by a second distance in the direction, and the first distance may be shorter than the second distance.

公开(公告)号：US20220093489A1

公开(公告)日：2022-03-24

申请号：US17540303

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG HO DO ,  SEUNGYOUNG LEE

IPC: H01L23/48 ,  H01L27/02 ,  H01L27/088

Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

公开(公告)号：US20210384106A1

公开(公告)日：2021-12-09

申请号：US16947241

申请日：2020-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG HO DO ,  SEUNGYOUNG LEE

IPC: H01L23/48 ,  H01L27/088 ,  H01L27/02

Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

公开(公告)号：US20230307324A1

公开(公告)日：2023-09-28

申请号：US18327291

申请日：2023-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG HO DO ,  Seungyoung Lee

IPC: H01L23/48 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L27/0207 ,  H01L27/088

Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

公开(公告)号：US20220059449A1

公开(公告)日：2022-02-24

申请号：US17518627

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG HO DO

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

Abstract: Integrated circuit devices including standard cells are provided. The integrated devices may include a lower transistor region and an upper transistor region. The lower transistor region may include a lower active region, lower source/drain regions, and lower gate structures arranged alternately with the lower source/drain regions. The upper transistor region may include an upper active region, upper source/drain regions, and upper gate structures arranged alternately with the upper source/drain regions. The upper gate structures may include a first upper gate structure. The integrated devices may also include an input wire, an input via electrically connecting the input wire to the first upper gate structure, and a routing wire electrically connecting a pair of the lower source/drain regions or a pair of the upper source/drain regions. An upper surface of the routing wire may be closer to the substrate than an upper surface of the input wire.

公开(公告)号：US20210242202A1

公开(公告)日：2021-08-05

申请号：US16947692

申请日：2020-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG HO DO ,  SEUNG HYUN SONG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Integrated circuit devices including standard cells are provided. The standard cells may include a first vertical field effect transistor (VFET) including a first channel region and having a first conductivity type and a second VFET including a second channel region and having a second conductivity type that is different from the first conductivity type. Each of the first channel region and the second channel region may extend longitudinally in a first horizontal direction, and the first channel region may be spaced apart from the second channel region in a second horizontal direction that is perpendicular to the first horizontal direction.