公开(公告)号：US20150380553A1

公开(公告)日：2015-12-31

申请号：US14673519

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KEUM SEOK PARK ,  JUNGHO YOO ,  JINYEONG JOE ,  BONYOUNG KOO ,  DONGSUK SHIN ,  HONGSIK YOON ,  BYEONGCHAN LEE

IPC: H01L29/78 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the, first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Abstract translation: 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

公开(公告)号：US20150206956A1

公开(公告)日：2015-07-23

申请号：US14499922

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  JUNGHO YOO ,  BYEONGCHAN LEE ,  Choeun LEE ,  HYUN JUNG LEE ,  Seong Hoon JEONG ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。