公开(公告)号：US20240106441A1

公开(公告)日：2024-03-28

申请号：US18466438

申请日：2023-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Min LEE ,  Gyu Sik KIM ,  Seung Jin KIM ,  Jae Hong JUNG

IPC: H03L7/093 ,  G05F3/26 ,  H03L1/00 ,  H03L7/099

CPC classification number: H03L7/093 ,  G05F3/262 ,  H03L1/00 ,  H03L7/0995

Abstract: A phase locked loop circuit and a semiconductor device are provided. The phased locked loop circuit includes a reference current generator configured to generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and output the summed compensation current as a reference current, a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code and a voltage control oscillator configured to generate a signal based on the control current, wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.