PHASE LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

    公开(公告)号:US20240106441A1

    公开(公告)日:2024-03-28

    申请号:US18466438

    申请日:2023-09-13

    CPC classification number: H03L7/093 G05F3/262 H03L1/00 H03L7/0995

    Abstract: A phase locked loop circuit and a semiconductor device are provided. The phased locked loop circuit includes a reference current generator configured to generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and output the summed compensation current as a reference current, a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code and a voltage control oscillator configured to generate a signal based on the control current, wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.

    SUBSTRATE PROCESSING APPARATUS
    3.
    发明公开

    公开(公告)号:US20240312765A1

    公开(公告)日:2024-09-19

    申请号:US18599825

    申请日:2024-03-08

    CPC classification number: H01J37/32183 H01J37/3299 H01J2237/24564

    Abstract: A substrate processing apparatus including the controller are provided. The controller includes: a signal analyzer configured to detect at least one of an amplitude, phase, and frequency of a first signal, which is provided to a chamber; a radio frequency (RF) signal generator configured to generate an RF signal with a natural frequency based on a power of the first signal; a harmonic controller configured to generate a second signal based on the power of the first signal and at least one of the amplitude, phase, and frequency of the first signal, the second signal having a different amplitude, a different phase, and/or a different frequency from the RF signal; an operator configured to perform an operation on the RF signal and the second signal; and a filter configured to generate an RF control signal by filtering an output signal of the operator.

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