公开(公告)号：US20230254388A1

公开(公告)日：2023-08-10

申请号：US18299972

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younho JEON ,  Hyeokjun CHOE ,  Jeongho LEE

IPC: H04L69/22 ,  H04L69/04 ,  H04L69/08

CPC classification number: H04L69/22 ,  H04L69/04 ,  H04L69/08

Abstract: An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.

公开(公告)号：US20220147476A1

公开(公告)日：2022-05-12

申请号：US17368981

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heehyun NAM ,  Jeongho LEE ,  Wonseb JEONG ,  Ipoom JEONG ,  Hyeokjun CHOE

IPC: G06F13/28 ,  G06F3/06

Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.

公开(公告)号：US20210407962A1

公开(公告)日：2021-12-30

申请号：US17154789

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongwon KIM ,  Junmo KOO ,  Yeonjoo KIM ,  Yunhee KIM ,  Jongkook KIM ,  Doohwan LEE ,  Jeongho LEE

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer.

公开(公告)号：US20210407924A1

公开(公告)日：2021-12-30

申请号：US17306555

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Doohwan LEE

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

公开(公告)号：US20210233859A1

公开(公告)日：2021-07-29

申请号：US16990717

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu LEE ,  Jingu KIM ,  Kyungdon MUN ,  Shanghoon SEO ,  Jeongho LEE

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

公开(公告)号：US20230325277A1

公开(公告)日：2023-10-12

申请号：US18335375

申请日：2023-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun CHOE ,  Heehyun NAM ,  Jeongho LEE ,  Younho JEON

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F3/0679 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0619

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

公开(公告)号：US20220164286A1

公开(公告)日：2022-05-26

申请号：US17408767

申请日：2021-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb JEONG ,  Heehyun NAM ,  Jeongho LEE

IPC: G06F12/0806 ,  G06F12/0862 ,  G06F12/02

Abstract: A device includes: a first interface circuit configured to communicate with a host processor; a second interface circuit configured to communicate with a memory comprising a plurality of storage regions; a cache memory including a plurality of cache lines configured to temporarily store data; and a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information.

公开(公告)号：US20220156146A1

公开(公告)日：2022-05-19

申请号：US17510898

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun CHOE ,  Heehyun NAM ,  Jeongho LEE ,  Younho JEON

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

公开(公告)号：US20220068424A1

公开(公告)日：2022-03-03

申请号：US17318234

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongho LEE ,  Kwangjin LEE ,  Hee Hyun NAM ,  Jaeho SHIN ,  Youngkwang YOO

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10

Abstract: Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.

公开(公告)号：US20220121574A1

公开(公告)日：2022-04-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.