公开(公告)号：US20180338279A1

公开(公告)日：2018-11-22

申请号：US16049186

申请日：2018-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghae CHOI ,  Hanseok KIM ,  Seongyong PARK ,  Jeongjae WON ,  Junsung LEE

IPC: H04W52/02 ,  G06F1/12 ,  H04L5/00

Abstract: A digital signal processing device of a base station configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA) and a method of processing data in the device are provided. The device includes a clock controller configured to monitor whether a signal is allocated to an input and control a frequency of clocks to have a first or second characteristic based on the monitored result, and a data processor configured to process the input, and synchronize with the clock controlled by the clock controller.

公开(公告)号：US20160286481A1

公开(公告)日：2016-09-29

申请号：US15075627

申请日：2016-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghae CHOI ,  Hanseok KIM ,  Seongyong PARK ,  Jeongjae WON ,  Junsung LEE

IPC: H04W52/02 ,  G06F1/12 ,  H04L5/00

CPC classification number: H04W52/0206 ,  G06F1/12 ,  H04L5/0048 ,  H04W52/0225 ,  H04W52/029 ,  Y02D70/00 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/146 ,  Y02D70/168

Abstract: A digital signal processing device of a base station configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA) and a method of processing data in the device are provided. The device includes a clock controller configured to monitor whether a signal is allocated to an input and control a frequency of clocks to have a first or second characteristic based on the monitored result, and a data processor configured to process the input, and synchronize with the clock controlled by the clock controller.

Abstract translation: 提供了一种被配置为在采用正交频分多址（OFDMA）的无线通信系统中处理下行链路信号的基站的数字信号处理装置和该装置中的数据处理方法。 所述设备包括：时钟控制器，被配置为监视信号是否被分配给输入，并且基于所监视的结果控制时钟的频率以具有第一或第二特性;以及数据处理器，被配置为处理所述输入，并与 时钟由时钟控制器控制。