公开(公告)号：US20250081457A1

公开(公告)日：2025-03-06

申请号：US18426564

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongyoon YEO ,  Joonsung KIM ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a gate stack including conductive patterns and interlayer insulating patterns, which are alternately stacked with each other, a channel layer surrounded by the gate stack, a memory layer surrounding the channel layer, a source structure electrically connected to the channel layer, and an insulating pattern between the memory layer and the source structure. The memory layer and the source structure are spaced apart from each other, and the insulating pattern is in contact with the channel layer, the memory layer, and the source structure.