公开(公告)号：US20250107086A1

公开(公告)日：2025-03-27

申请号：US18737295

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanbyeol LEE ,  Younghwan SON ,  Sangdon LEE ,  Shinhwan KANG ,  Sukkang SUNG

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.

公开(公告)号：US20210066344A1

公开(公告)日：2021-03-04

申请号：US16850244

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON ,  Seungwon LEE ,  Seogoo KANG ,  Juyoung LIM ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/49 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56

Abstract: A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.

公开(公告)号：US20210036011A1

公开(公告)日：2021-02-04

申请号：US16844429

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan SON ,  Seogoo KANG ,  Jeehoon HAN

IPC: H01L27/11582 ,  G11C8/14 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure.

公开(公告)号：US20250087584A1

公开(公告)日：2025-03-13

申请号：US18666962

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyung KIM ,  Chulhae PARK ,  Younghwan SON ,  Sukkang SUNG

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor structure including, circuit devices on a substrate, a lower interconnection structure, and a capacitor structure on a same level as a level of at least a portion of the lower interconnection structure, and a second semiconductor structure on the first semiconductor structure and including a plurality of memory cells arranged three-dimensionally. The lower interconnection structure includes a lower contact, a lower line on the lower contact, an upper contact on the lower line, and an upper line on the upper contact. The capacitor structure includes first electrode structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, second electrode structures positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction, and dielectric layers between the first electrode structures and the second electrode structures.

公开(公告)号：US20250081457A1

公开(公告)日：2025-03-06

申请号：US18426564

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongyoon YEO ,  Joonsung KIM ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a gate stack including conductive patterns and interlayer insulating patterns, which are alternately stacked with each other, a channel layer surrounded by the gate stack, a memory layer surrounding the channel layer, a source structure electrically connected to the channel layer, and an insulating pattern between the memory layer and the source structure. The memory layer and the source structure are spaced apart from each other, and the insulating pattern is in contact with the channel layer, the memory layer, and the source structure.

公开(公告)号：US20210098479A1

公开(公告)日：2021-04-01

申请号：US16893524

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON ,  Boyoung LEE ,  Seoungwon LEE ,  Seunghwan LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06

Abstract: A vertical non-volatile memory device includes a stack body including gate patterns and interlayer insulating patterns stacked in a stacking direction, the stack body having a through hole, which extends in the stacking direction, in the gate patterns and in the interlayer insulating patterns; a semiconductor pillar in the through hole and extending in the stacking direction; data storage structures between the gate patterns and the semiconductor pillar in the through hole, the data storage structures including charge storage layers; and dummy charge storage layers on a sidewall of the interlayer insulating patterns toward the semiconductor pillar in the through hole.

公开(公告)号：US20250072001A1

公开(公告)日：2025-02-27

申请号：US18800667

申请日：2024-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeol LEE ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes: a peripheral circuit structure including a substrate and a circuit that is disposed on the substrate; a cell structure disposed on the peripheral circuit structure and including gate electrodes and a channel that extends through the gate electrodes; and a bonding structure located between the peripheral circuit structure and the cell structure, wherein the bonding structure includes: a first insulating layer attached to the peripheral circuit structure; a first bonding pad disposed on the peripheral circuit structure and electrically connected to the circuit; a second insulating layer attached to the cell structure; a second bonding pad disposed on the cell structure and electrically connected to the gate electrodes; and an anisotropic conductive adhesive layer located between the first insulating layer and the second insulating layer and between the first bonding pad and the second bonding pad, and including a plurality of conductive particles.

公开(公告)号：US20240224521A1

公开(公告)日：2024-07-04

申请号：US18428264

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20230200072A1

公开(公告)日：2023-06-22

申请号：US17876877

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON ,  Dongkeun LEE

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Provided is a method including forming a mold structure including insulating layers and sacrificial layers alternately stacked on a semiconductor substrate, the insulating layers exposing stepwise-stacked ends of the sacrificial layers on a connection region of the semiconductor substrate, forming a sacrificial oxide layer to cover the exposed ends , forming sacrificial pad patterns on the exposed ends, respectively, forming a planarization insulating layer to cover the sacrificial oxide layer and the sacrificial pad patterns, forming a vertical contact hole to penetrate the planarization insulating layer, each of the sacrificial pad patterns, the sacrificial oxide layer and the mold structure, removing each of the sacrificial pad patterns to form a recess region, removing a portion of the sacrificial oxide layer exposed by the recess region to form an extended recess region, and forming a cell contact plug to fill the vertical contact hole and the extended recess region.

公开(公告)号：US20220392916A1

公开(公告)日：2022-12-08

申请号：US17679268

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon BAEK ,  Miram KWON ,  Seongjun SEO ,  Younghwan SON

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/06

Abstract: A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.