公开(公告)号：US20240224514A1

公开(公告)日：2024-07-04

申请号：US18498673

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H10B41/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: An integrated circuit device includes a substrate including a memory cell area and a connection area, a gate stack including a plurality of gate electrodes apart from each other in a vertical direction on the substrate, a plurality of gate connection openings arranged in the connection area to extend inward from an upper surface of the gate stack, one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings, a plurality of gate connection structures respectively covering at least inner side surfaces of the plurality of gate connection openings, each of the plurality of gate connection structures being connected with the one gate electrode, and a plurality of gate contacts respectively connected to upper ends of the plurality of gate connection structures.

公开(公告)号：US20240203943A1

公开(公告)日：2024-06-20

申请号：US18346921

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Jiwon KIM ,  Minyong LEE ,  Dohyung KIM ,  Sukkang SUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/528 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/80379 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: The inventive concept provides a chip stack structure including a first semiconductor chip and a second semiconductor chip bonded to each other, and a semiconductor package including a plurality of chip stack structures stacked in a vertical direction.

公开(公告)号：US20220130846A1

公开(公告)日：2022-04-28

申请号：US17239829

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwon KIM ,  Jaeho AHN ,  Sungmin HWANG ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L27/11556 ,  H01L23/522 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/78

Abstract: A semiconductor device including a cell area including a first substrate, gate electrodes on the first substrate, a channel structure extending through the gate electrodes, cell contact plugs, a through contact plug, and first bonding pads, the first peripheral circuit area including second bonding pads on the first bonding pads; a second peripheral circuit area connected to the first peripheral circuit area; and a second substrate between the first peripheral circuit area and the second peripheral circuit area, the second substrate including a first surface in the first peripheral circuit area and a second surface in the second peripheral circuit area, wherein the second peripheral circuit area includes a device on the second surface, and a through electrode extending vertically through the second substrate and connected to the first peripheral circuit area.

公开(公告)号：US20250107086A1

公开(公告)日：2025-03-27

申请号：US18737295

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanbyeol LEE ,  Younghwan SON ,  Sangdon LEE ,  Shinhwan KANG ,  Sukkang SUNG

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.

公开(公告)号：US20240315023A1

公开(公告)日：2024-09-19

申请号：US18489451

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Woosung YANG ,  Jimo GU ,  Sukkang SUNG

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5223 ,  H10B41/27

Abstract: Disclosed are semiconductor devices which may include a substrate having first and second regions, a stack structure including electrode patterns and dielectric patterns, channels vertically penetrating the stack structure on the first region, a planarized dielectric layer covering the stack structure, and wiring patterns on the planarized dielectric layer. The dielectric pattern includes a first dielectric pattern on the first region, and a second dielectric pattern on the second region. The second dielectric pattern includes a first sub-dielectric pattern and a second sub-dielectric pattern. A dielectric constant of the first sub-dielectric patterns is greater than that of the first dielectric patterns and that of the second sub-dielectric patterns.

公开(公告)号：US20240074203A1

公开(公告)日：2024-02-29

申请号：US18357401

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek JUNG ,  Sukkang SUNG

IPC: H10B43/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H10B43/27

Abstract: A semiconductor device may include a peripheral circuit structure including cell region and an outside region, a cell structure on the cell region, an outside structure on the outside region, and an insulating layer. The outside structure may include a dummy stacked structure, a through electrode penetrating the dummy stacked structure and connected to the peripheral circuit structure, and a dummy vertical structure adjacent to the through electrode and penetrating at least a portion of the dummy stacked structure. The insulating layer may be between the dummy stacked structure and the peripheral circuit structure. The dummy stacked structure may include an upper dummy stacked structure on a lower dummy stacked structure. The upper dummy stacked structure may include upper dummy patterns stacked on the lower dummy stacked structure. The lower dummy stacked structure may include lower dummy patterns stacked on the outside region.

公开(公告)号：US20230326847A1

公开(公告)日：2023-10-12

申请号：US18334546

申请日：2023-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/2105 ,  H01L2224/24146 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B43/27

Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

公开(公告)号：US20230109996A1

公开(公告)日：2023-04-13

申请号：US17955696

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon SON ,  Sukkang SUNG ,  Sangdon LEE ,  Euntaek JUNG

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A vertical non-volatile memory device includes, a substrate, a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate, a plurality of insulating layers between the gate lines, a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate, and a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.

公开(公告)号：US20220375959A1

公开(公告)日：2022-11-24

申请号：US17552812

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdon LEE ,  Jiwon KIM ,  Sung-Min HWANG ,  Sukkang SUNG

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.

公开(公告)号：US20250072001A1

公开(公告)日：2025-02-27

申请号：US18800667

申请日：2024-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeol LEE ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes: a peripheral circuit structure including a substrate and a circuit that is disposed on the substrate; a cell structure disposed on the peripheral circuit structure and including gate electrodes and a channel that extends through the gate electrodes; and a bonding structure located between the peripheral circuit structure and the cell structure, wherein the bonding structure includes: a first insulating layer attached to the peripheral circuit structure; a first bonding pad disposed on the peripheral circuit structure and electrically connected to the circuit; a second insulating layer attached to the cell structure; a second bonding pad disposed on the cell structure and electrically connected to the gate electrodes; and an anisotropic conductive adhesive layer located between the first insulating layer and the second insulating layer and between the first bonding pad and the second bonding pad, and including a plurality of conductive particles.