公开(公告)号：US20170221893A1

公开(公告)日：2017-08-03

申请号：US15390361

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk TAK ,  Tae-jong LEE ,  Gi-gwan PARK ,  Ji-myoung LEE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/02 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42376

Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.