公开(公告)号：US20190287629A1

公开(公告)日：2019-09-19

申请号：US16154111

申请日：2018-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Seung Hwan SONG ,  Dae Seok BYEON ,  II Han PARK ,  Hyun Jun YOON ,  Han Jun LEE ,  Na Young CHOI

IPC: G11C16/28 ,  G11C11/56 ,  G06F11/10 ,  G06F3/06

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US20200265908A1

公开(公告)日：2020-08-20

申请号：US16865675

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Seung Hwan SONG ,  Dae Seok BYEON ,  Il Han PARK ,  Hyun Jun YOON ,  Han Jun LEE ,  Na Young CHOI

IPC: G11C27/00 ,  G11C16/28 ,  G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G06F11/10

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US20190295671A1

公开(公告)日：2019-09-26

申请号：US16157579

申请日：2018-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Joon Suc JANG

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56

Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.