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公开(公告)号:US20250081865A1
公开(公告)日:2025-03-06
申请号:US18818913
申请日:2024-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: JINWOO LEE , Hyunsang Hwang , Youngdong Kim , DONGHO AHN , Jin Myung Choi , Geon Hui Han
Abstract: A memory device comprising a stacking structure including a plurality of electrodes and an insulation layer between the plurality of electrodes. The stacking structure has a recess portion corresponding to the plurality of electrodes or the insulation layer at a side surface of the stacking structure. The memory device also comprising a resistance variable layer on the side surface of the stacking structure having the recess portion, and includes a portion extending in an extension direction crossing the stacking structure. The resistance variable layer includes a first portion including a first expanded portion along a recess surface of the recess portion, a second portion including a second expanded portion along the recess surface of the recess portion on the first portion, and a third portion on the second portion. The second portion has a resistance smaller than a resistance of the first portion.
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公开(公告)号:US20240365567A1
公开(公告)日:2024-10-31
申请号:US18471585
申请日:2023-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinwoo Lee , Dongho Ahn , Jin Myung Choi
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: A semiconductor device according to an embodiment includes a gate stack structure and a channel structure. The gate stack structure includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on a substrate in a first direction perpendicular to an upper surface of the substrate. The channel structure includes a portion penetrating through the gate stack structure and extending in the first direction. The channel structure includes a channel layer, a resistance change layer, and a metal-containing layer sequentially stacked. The metal-containing layer includes a metal or a metal compound.
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