公开(公告)号：US20240244835A1

公开(公告)日：2024-07-18

申请号：US18517325

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taiuk RIM ,  Jinseong LEE ,  Kyosuk CHAE

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral circuit region, a first gate structure in the cell region of the substrate, the first gate structure extending in a first direction parallel to an upper surface of the substrate, bit line structures on the cell region of the substrate, the bit line structures extending in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate, a second gate structure on the peripheral circuit region of the substrate, contact plug structures between the bit line structures, the contact plug structures contacting the substrate, first conductive structures on peripheral circuit region of the substrate, the first conductive structures being electrically connected to the peripheral circuit region of the substrate, a first upper insulation structure between the first conductive structures, the first upper insulation structure including a first upper insulation pattern and a hydrogen diffusing insulation pattern surrounding a bottom and sidewalls of the first upper insulation pattern, and a second upper insulation pattern between upper portions of the contact plug structures.

公开(公告)号：US20230109983A1

公开(公告)日：2023-04-13

申请号：US17724685

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinseong LEE ,  Kyounghee KIM ,  Dongsoo WOO ,  Kyosuk CHAE

IPC: H01L27/108

Abstract: A semiconductor device including a cell active pattern; a cell gate structure connected to the cell active pattern; a peripheral active pattern; a peripheral gate structure connected to the peripheral active pattern; a conductive pattern connected to the peripheral active pattern, the cell gate structure, or the peripheral gate structure; a capacitor structure electrically connected to the cell active pattern; an interlayer insulating layer surrounding the capacitor structure; and a peripheral contact connected to the conductive pattern while extending through the interlayer insulating layer, wherein the interlayer insulating layer includes a first material layer contacting the capacitor structure, and a second material layer on the first material layer, the peripheral contact includes a first portion contacting the first material layer, and a second portion contacting the second material layer, and a maximum width of the first portion is greater than a minimum width of the second portion.