公开(公告)号：US20230024307A1

公开(公告)日：2023-01-26

申请号：US17590087

申请日：2022-02-01

申请人： Samsung Electronics Co., Ltd

发明人： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO

IPC分类号： H01L27/11507

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a substrate; a transistor disposed above the substrate, the transistor having a channel region defining an inner space; and a capacitor passing through the transistor in a vertical direction in the inner space.

公开(公告)号：US20220367479A1

公开(公告)日：2022-11-17

申请号：US17716215

申请日：2022-04-08

申请人： Samsung Electronics Co., Ltd.

发明人： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Dongsoo WOO ,  Sungwon YOO

IPC分类号： H01L27/108 ,  H01L29/423 ,  H01L29/792

摘要： A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

公开(公告)号：US20200381436A1

公开(公告)日：2020-12-03

申请号：US16744871

申请日：2020-01-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyungjun NOH ,  Junsoo KIM ,  Dongsoo WOO ,  Namho JEON

IPC分类号： H01L27/108 ,  H01L23/528 ,  H01L29/51 ,  H01L21/265 ,  H01L21/3115

摘要： An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

公开(公告)号：US20210057416A1

公开(公告)日：2021-02-25

申请号：US17090419

申请日：2020-11-05

申请人： Samsung Electronics Co., Ltd.

发明人： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L27/108 ,  H01L27/06 ,  H01L49/02

摘要： Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20190198626A1

公开(公告)日：2019-06-27

申请号：US16288910

申请日：2019-02-28

申请人： Samsung Electronics Co., Ltd.

发明人： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC分类号： H01L29/40 ,  H01L27/108 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/84

CPC分类号： H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

摘要： A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20150055401A1

公开(公告)日：2015-02-26

申请号：US14537387

申请日：2014-11-10

申请人： Samsung Electronics Co., Ltd.

发明人： Jiyoung KIM ,  Yongchul OH ,  Dongsoo WOO ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  Sungkwan CHOI ,  Hyeongsun HONG ,  Yoosang HWANG

IPC分类号： G11C11/4096 ,  G11C11/404 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US20240105790A1

公开(公告)日：2024-03-28

申请号：US18337952

申请日：2023-06-20

申请人： Samsung Electronics Co., Ltd.

发明人： Joonsoo PARK ,  Bongjin KUH ,  Bongsoo KIM ,  Yoonjae KIM ,  Dongsoo WOO

IPC分类号： H01L29/423 ,  H10B12/00

CPC分类号： H01L29/4236 ,  H01L28/60 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

摘要： Provided is an integrated circuit device including a substrate including a first active area and a second active area each extending in a first direction, a bit line extending in the first direction in a first trench of the substrate and arranged between the first active area and the second active area in a second direction perpendicular to the first direction, a contact structure including a lower contact contacting the bit line and an upper contact contacting the first active area, a word line extending in the second direction in a second trench of the substrate, a plurality of landing pads on the substrate, and a capacitor structure including a plurality of lower electrodes on the plurality of landing pads, wherein the bit line and the word line are buried under an upper surface of the substrate.

公开(公告)号：US20230109983A1

公开(公告)日：2023-04-13

申请号：US17724685

申请日：2022-04-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jinseong LEE ,  Kyounghee KIM ,  Dongsoo WOO ,  Kyosuk CHAE

IPC分类号： H01L27/108

摘要： A semiconductor device including a cell active pattern; a cell gate structure connected to the cell active pattern; a peripheral active pattern; a peripheral gate structure connected to the peripheral active pattern; a conductive pattern connected to the peripheral active pattern, the cell gate structure, or the peripheral gate structure; a capacitor structure electrically connected to the cell active pattern; an interlayer insulating layer surrounding the capacitor structure; and a peripheral contact connected to the conductive pattern while extending through the interlayer insulating layer, wherein the interlayer insulating layer includes a first material layer contacting the capacitor structure, and a second material layer on the first material layer, the peripheral contact includes a first portion contacting the first material layer, and a second portion contacting the second material layer, and a maximum width of the first portion is greater than a minimum width of the second portion.

公开(公告)号：US20230049653A1

公开(公告)日：2023-02-16

申请号：US17722672

申请日：2022-04-18

申请人： Samsung Electronics Co., Ltd.

发明人： Kyunghwan LEE ,  Yongseok KIM ,  Dongsoo WOO ,  Junhee LIM

IPC分类号： H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

摘要： A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

公开(公告)号：US20180158918A1

公开(公告)日：2018-06-07

申请号：US15868620

申请日：2018-01-11

申请人： Samsung Electronics Co., Ltd.

发明人： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC分类号： H01L29/40 ,  H01L27/108 ,  H01L29/423

CPC分类号： H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

摘要： A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.