公开(公告)号：US20250167174A1

公开(公告)日：2025-05-22

申请号：US18737484

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunseok YANG ,  Yunsang Lee ,  Minsoo Kim ,  Jaewoo Shin ,  Minhwan An ,  Yunkyeong Jeong ,  Jinsuk Chung

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/28 ,  H01L23/48 ,  H01L23/498 ,  H10B80/00

Abstract: A semiconductor package includes a plurality of first semiconductor chips sequentially stacked in a vertical direction, and connected to each other via a plurality of first through electrodes, each of the plurality of first semiconductor chips having a first width in a horizontal direction, a second semiconductor chip under the plurality of first semiconductor chips, and connected to the plurality of first semiconductor chips via a plurality of second through electrodes, the second semiconductor chip having a second width in the horizontal direction, the second width being greater than the first width, a redistribution layer under the second semiconductor chip, the redistribution layer having a third width in the horizontal direction, the third width being substantially equal to the second width, and a plurality of first connection bumps between the second semiconductor chip and the redistribution layer.

公开(公告)号：US20240196633A1

公开(公告)日：2024-06-13

申请号：US18529365

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseok Yang ,  Seula Ryu ,  Jaewoo Shin ,  Minhwan An ,  Seongjin Lee ,  Sunghak Lee ,  Eungchang Lee ,  Yunkyeong Jeong ,  Jinsuk Chung

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A memory device and a system includes a plurality of physical interfaces. The memory device includes a buffer die including a first interface circuit and a second interface circuit configured to communicate with an external device and a memory die stack mounted on the buffer die and including a plurality of stacked memory dies. The plurality of memory dies are electrically connected to the first interface circuit and the second interface circuit, the first interface circuit is configured to activate responsive to a first selection signal, and the second interface circuit is configured to activate responsive to a second selection signal. The first selection signal and the second selection signal are received from a memory controller external to the memory device.