利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.016 秒)

    Input buffer
    2.
    发明授权
    Input buffer 有权
    输入缓冲区

    公开(公告)号：US08891329B2

    公开(公告)日：2014-11-18

    申请号：US13835244

    申请日：2013-03-15

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yunseok Yang

    IPC分类号： G11C7/22 ,  H03K19/003

    CPC分类号： H03K19/00384

    摘要： An input buffer includes a first buffer circuit to amplify a difference between a first input signal and a second input signal; a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal; and a detector to compare the common mode output signal with a reference output signal and to control the first and second buffer circuits according to the comparison result such that a level of the common mode output signal coincides with a level of the reference output signal.

    摘要翻译： 输入缓冲器包括用于放大第一输入信号和第二输入信号之间的差的第一缓冲电路; 第二缓冲电路，由第一缓冲电路的复制电路构成，以响应于第一输入信号产生共模输出信号; 以及检测器，用于将共模输出信号与参考输出信号进行比较，并根据比较结果控制第一和第二缓冲电路，使得共模输出信号的电平与参考输出信号的电平一致。

    Nonvolatile memory device including sudden power off detection circuit and sudden power off detection method thereof
    3.
    发明授权
    Nonvolatile memory device including sudden power off detection circuit and sudden power off detection method thereof 有权
    非易失性存储装置，包括突然断电检测电路和突然断电检测方法

    公开(公告)号：US08873328B2

    公开(公告)日：2014-10-28

    申请号：US14037544

    申请日：2013-09-26

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yong Shik Shin ,  Yunseok Yang ,  Oh-Seong Kwon

    IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C5/14 ,  G11C11/16

    CPC分类号： G11C11/1697 ,  G11C5/143 ,  G11C11/1675

    摘要： A nonvolatile memory device includes a memory cell array comprising memory cells connected to bit lines and word lines; a word line decoder configured to apply word line voltages to the word lines; a bit line selector configured to select at least one bit line of the bit lines; a control logic configured to control the word line decoder and the bit line selector so that write data is programmed in the memory cell array; and a sudden power off (SPO) detection circuit, wherein the SPO detection circuit comprises: a sensing cell; a first driver configured to provide a first voltage to the sensing cell; and a second driver configured to provide a second voltage to the sensing cell, wherein a program state of the sensing cell becomes different depending on an order or a time difference between the first driver and the second driver being powered off.

    摘要翻译： 非易失性存储器件包括存储单元阵列，其包括连接到位线和字线的存储单元; 字线解码器，被配置为将字线电压施加到所述字线; 配置为选择位线的至少一个位线的位线选择器; 控制逻辑，被配置为控制字线解码器和位线选择器，使得写入数据被编程在存储单元阵列中; 和突发断电（SPO）检测电路，其中SPO检测电路包括：感测单元; 第一驱动器，被配置为向所述感测单元提供第一电压; 以及第二驱动器，被配置为向所述感测单元提供第二电压，其中所述感测单元的编程状态根据所述第一驱动器和所述第二驱动器被断电的顺序或时间差而变得不同。