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1.发明公开公开(公告)号：US20240171186A1
公开(公告)日：2024-05-23
申请号：US18422192
申请日：2024-01-25
发明人： Youngsea CHO , Wan KIM , Jiseon PAEK , Seunghyun OH
IPC分类号： H03M1/06
CPC分类号： H03M1/0617 , H03M1/66
摘要： A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.
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2.发明申请公开(公告)号：US20200310477A1
公开(公告)日：2020-10-01
申请号：US16582401
申请日：2019-09-25
发明人： Ikhwan KIM , Nomiyama TAKAHIRO , Jiseon PAEK , Jaeyeol HAN
摘要： A regulating circuit including a first direct current (DC)-DC converter configured to apply a first supply voltage to a first node in a first mode and apply the first supply voltage to a second node in a second mode, a first low drop output (LDO) regulator connected to the first node, the first LDO regulator configured to provide an output voltage to an output node by regulating the first supply voltage of the first node, and a second LDO regulator connected to the first node, the second LDO regulator configured to provide an auxiliary current to the first node in the second mode may be provided.
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3.发明申请公开(公告)号：US20220060114A1
公开(公告)日：2022-02-24
申请号：US17521187
申请日：2021-11-08
发明人： Ikhwan KIM , Nomiyama TAKAHIRO , Jiseon PAEK , Jaeyeol HAN
摘要： A regulating circuit including a first direct current (DC)-DC converter configured to apply a first supply voltage to a first node in a first mode and apply the first supply voltage to a second node in a second mode, a first low drop output (LDO) regulator connected to the first node, the first LDO regulator configured to provide an output voltage to an output node by regulating the first supply voltage of the first node, and a second LDO regulator connected to the first node, the second LDO regulator configured to provide an auxiliary current to the first node in the second mode may be provided.
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公开(公告)号：US20210367630A1
公开(公告)日：2021-11-25
申请号：US17215503
申请日：2021-03-29
发明人： Youngsea CHO , Jiseon PAEK , Wan KIM , Daechul JEONG
摘要： A radio frequency (RF) transmitter including a switched-capacitor digital-to-analog converter (SC-DAC) configured to selectively generate a first RF output signal having a first output power control range or a second RF output signal having a second output power control range from input signals received through a plurality of lines may be provided.
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公开(公告)号：US20220376698A1
公开(公告)日：2022-11-24
申请号：US17560400
申请日：2021-12-23
发明人： Youngsea CHO , Wan KIM , Jiseon PAEK , Seunghyun OH
摘要： Provided are an analog-to-digital converter and/or an operating method thereof. The analog-to-digital converter includes a sample/hold circuit, a digital-to-analog converter, a comparing circuit, and a control logic circuit, wherein the digital-to-analog converter includes a first capacitor connected to a first comparison node and a first filtering node, a first reference voltage switch connected to the first filtering node and connected to a first delivery node or a first transmission node, a first pre-charge switch connected to the first filtering node or the first delivery node, and a first pre-charge capacitor connected to the first pre-charge switch and a ground voltage.
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公开(公告)号：US20210367624A1
公开(公告)日：2021-11-25
申请号：US17196463
申请日：2021-03-09
发明人： Youngsea CHO , Jiseon PAEK , Wan KIM , Daechul JEONG
摘要： A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.
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