公开(公告)号：US10431320B2

公开(公告)日：2019-10-01

申请号：US15394973

申请日：2016-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Shin Kwon ,  Jong-Hyoung Lim ,  Chang-Soo Lee ,  Chung-Ki Lee

IPC: G11C29/12 ,  G11C8/08 ,  G11C16/34 ,  G11C29/08 ,  G11C29/10 ,  G11C29/18 ,  G11C7/12

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.

公开(公告)号：US09159398B2

公开(公告)日：2015-10-13

申请号：US14147545

申请日：2014-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Il Mok ,  Jong-Hyoung Lim ,  Dae-Sun Kim ,  Ji-Hyun Lee

IPC: G11C7/00 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4076 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.

Abstract translation: 半导体器件可以包括连接到位线和第一字线的第一存储器单元，连接到互补位线和第二字线的第二存储器单元以及均衡器。 均衡器可以被配置为当位线和互补位线浮置时在第一时间段将位线和互补位线的电压从第一电压转换到不同于第一电压的第二电压， 并且当所述位线和互补位线浮置时，在所述第一时间段之后的第二时间周期将所述位线和所述互补位线中的至少一个的电压从所述第二电压转换到第三电压， 第三电压与第一和第二电压不同。