公开(公告)号：US20190310905A1

公开(公告)日：2019-10-10

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong KO ,  Dae-Jeong KIM ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Yongjun YU ,  lnsu CHOI ,  Hui-Chung BYUN ,  JongYoung LEE

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.