公开(公告)号：US20240004757A1

公开(公告)日：2024-01-04

申请号：US18295457

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Young LEE ,  Sung-Joon KIM ,  IIho KIM ,  Kyungjin PARK ,  Changho YUN ,  Jinhun JEONG ,  Insu CHOI ,  Kyung-Hee HAN ,  Yukyoung KIM ,  Jinwoo KIM ,  Chaeeun LEE ,  Yunmi HWANG

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0793

Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

公开(公告)号：US20190206494A1

公开(公告)日：2019-07-04

申请号：US16174839

申请日：2018-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Su HAN ,  Sung-Joon KIM ,  Jong-Hwa KIM ,  Da-Hee JEONG

IPC: G11C16/10 ,  G11C16/08 ,  G11C7/10

Abstract: A non-volatile memory device includes a non-volatile memory cell array, an input/output pad unit, and a peripheral circuit. The non-volatile memory device executes an operation requested by a controller. The input/output pad component provides a path through which a command and data related to the operation requested by the controller are input to the non-volatile memory device, and through which a result of execution of the requested operation is output to the controller. The peripheral circuit is configured to be loaded with a plurality of commands provided by the controller, to temporarily store program data provided by the controller to be written in the non-volatile memory cell array and data read from the non-volatile memory cell array, to adjust an execution order of the commands asynchronously with the controller based on an internal operation status of the non-volatile memory device, and to execute the commands in the adjusted execution order.

公开(公告)号：US20190310905A1

公开(公告)日：2019-10-10

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong KO ,  Dae-Jeong KIM ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Yongjun YU ,  lnsu CHOI ,  Hui-Chung BYUN ,  JongYoung LEE

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US20190303282A1

公开(公告)日：2019-10-03

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong KIM ,  Jiseok KANG ,  Tae-Kyeong KO ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Wonjae SHIN ,  Yongjun YU ,  Insu CHOI

IPC: G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G11C11/56

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.