公开(公告)号：US20250151293A1

公开(公告)日：2025-05-08

申请号：US18738574

申请日：2024-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeehyun JUNG ,  Hansung RYU ,  Jongbeom PARK

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065

Abstract: A high bandwidth memory includes a base die and a memory stack on the base die. The memory stack includes a plurality of memory dies. The memory stack includes a first memory die closest to the base die among the plurality of memory dies and having a first width in a horizontal direction, and a second memory die on the first memory die and having a second width in the horizontal direction, the first width is smaller than the second width.

公开(公告)号：US20250132227A1

公开(公告)日：2025-04-24

申请号：US18621451

申请日：2024-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansung RYU ,  Jongbeom PARK

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip below the first semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a first semiconductor device and a first interconnection layer on a bottom surface of the first semiconductor substrate, a first via penetrating the first semiconductor substrate and electrically connected to the first interconnection layer, and a first pad on a bottom surface of the first interconnection layer. The second semiconductor chip may include a second semiconductor substrate, a second via penetrating the second semiconductor substrate, and a second pad on a top surface of the second semiconductor substrate and electrically connected to the second via. The first and second vias may be shifted from each other in a horizontal direction, and the first via may be horizontally spaced apart from the first pad, when viewed in a plan view.

公开(公告)号：US20240063077A1

公开(公告)日：2024-02-22

申请号：US18137809

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongbeom PARK ,  Hansung RYU ,  Kangjoon LEE

IPC: H01L23/367 ,  H01L25/18 ,  H10B80/00 ,  H01L23/00 ,  H01L23/427 ,  H01L23/433

CPC classification number: H01L23/367 ,  H01L25/18 ,  H10B80/00 ,  H01L24/06 ,  H01L24/05 ,  H01L24/16 ,  H01L24/17 ,  H01L23/427 ,  H01L23/433 ,  H01L25/0657

Abstract: A semiconductor package includes a package base substrate, a first semiconductor chip on the package base substrate, a second semiconductor chip on the package base substrate, and spaced apart from the first semiconductor chip in a first horizontal direction, a reinforcing structure on the package base substrate, and spaced apart from the second semiconductor chip in a second horizontal direction intersecting the first horizontal direction, and a heat transfer pad between the second semiconductor chip and the reinforcing structure.

公开(公告)号：US20230130356A1

公开(公告)日：2023-04-27

申请号：US17734424

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbeom PARK

IPC: H01L23/498

Abstract: A package substrate may include an insulation substrate, a plurality of upper pads, a plurality of first lower pads, a plurality of second lower pads and a plurality of patches. The insulation substrate may have a lower surface including a first region where external terminals may be mounted and a second region where an electronic component may be mounted. The first lower pads may be arranged in the first region. The second lower pads may be arranged in the second region. The patches may be arranged between the second lower pads in the second region to suppress a warpage of the electronic component. Thus, the warpage may not be generated at the electronic component to prevent a crack from being generated in the electronic component.