公开(公告)号：US20140043920A1

公开(公告)日：2014-02-13

申请号：US13962233

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hee SHIN ,  Young Man AHN ,  Seung Mo JUNG ,  You Keun HAN ,  Sang Jhun HWANG

IPC: G01R31/02 ,  G11C7/00

CPC classification number: G01R31/02 ,  G01R31/01 ,  G01R31/26 ,  G01R31/27 ,  G06F13/28 ,  G06F17/5054 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/1036 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/0401 ,  G11C2029/4002 ,  H03M7/40 ,  H03M13/00

Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.

Abstract translation: 存储器件包括存储单元阵列和数据输入/输出电路。 存储单元阵列包括连接到多个位线和多个字线的多个存储单元。 数据输入/输出电路被配置为从存储器件的外部数据引脚接收数据，通过电耦合到多个位线的多个输入/输出线将接收到的数据输出到存储单元阵列，从多个位线读取数据 通过多个输入/输出线的存储单元阵列，并通过外部数据引脚输出读取的数据。 对于每个外部数据引脚，数据输入/输出电路被配置为将在外部数据引脚处接收的数据输出到相应的输入/输出线。 响应于包含在接收数据中的一组位的位值来选择相应的输入/输出线。